Patent EP0268315A2 successfully refreshed from Google Patents.
EP0268315A2
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EP
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EEPROM memory cell with a single polysilicon level and a tunnel oxide zone
Assignee: STMicroelectronics SRL
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Filing: 1987-10-23
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Granted: —
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Expires: 2007-10-23
Abstract
Abstract The memory cell comprises a selection transistor (51), pickup transistor (52) and a tunnel condenser (53) formed using a single layer of polysilicon (59). The tunnel condenser (53) is formed on an active area (56) distinct and separate from that of the pickup transistor (52).
Inventors
- 👤 Carlo Riva
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
103 words
EEPROM memory cell comprising a selection transistor (51), a pickup transistor (52) with floating gate (62) and control gate (69), and a tunnel condenser (53) with thin oxide zone (58) formed using a single layer of polysilicon (59) for the floating gate (62) and the tunnel condenser (53) and at least one active area (55) with n⁺ diffusion (69) for the control gate characterized in that said thin oxide zone (58) of the tunnel condenser (53) is formed on an active area (56) distinct and separate from that of the pickup transistor (52) in series with said diffusion (69) of the control gate.
Claim 2
Dependent Claim
103 words
EEPROM memory cell comprising a selection transistor (51), a pickup transistor (52) with floating gate (62) and control gate (69), and a tunnel condenser (53) with thin oxide zone (58) formed using a single layer of polysilicon (59) for the floating gate (62) and the tunnel condenser (53) and at least one active area (55) with n⁺ diffusion (69) for the control gate characterized in that said thin oxide zone (58) of the tunnel condenser (53) is formed on an active area (56) distinct and separate from that of the pickup transistor (52) in series with said diffusion (69) of the control gate.
Claim 3
Dependent Claim
99 words
Memory cell in accordance with claim 1 characterized in that said single polysilicon layer comprises a first part (60) defining the gate of the selection transistor and a second part (68) formed of a first arm (61) superimposed on the thin oxide zone (58) on said distinct and separate active area (56), a second arm (62) superimposed on said at least one active area (55) to form the floating gate of the pickup transistor (52) and a space (63) further superimposed on said at least one active area (55) to form a coupling condenser of the control gate (69).
References Cited (Backward Citations)
No citation records indexed.
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