Patent EP0264929A2 successfully refreshed from Google Patents.
EP0264929A2
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Semiconductor memory device with improved bit line arrangement
Assignee: NEC Corp
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Filing: 1987-10-21
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Granted: —
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Expires: 2007-10-21
Abstract
Abstract A dynamic type semiconductor memory device with an improved bit line arrangement is disclosed. The memory device comprises at least first and second pairs of bit lines and a sense amplifier having a pair of input terminals to which one pair of bit lines among the first and second bit line pairs are selectively connected, and is featured in that the bit lines of the first bit line pair and the bit lines of the second bit line pair are alternately arranged in parallel.
Inventors
- 👤 Seiichi C/O Nec Corporation Hannai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
144 words
A semiconductor memory device comprising first to fourth bit lines arranged consecutively in parallel, first to fourth memory cells coupled to said first to fourth bit lines, respectively, first to fourth word lines coupled to said first to fourth memory cells, respectively, a sense amplifiers having a pair of input terminals, means for selecting one of said first to fourth word lines, a first transfer circuit for operatively connecting said first and third bit lines to said pair of input terminals of said sense amplifier, a second transfer circuit for operatively connecting said second and fourth bit lines to said pair of input terminals of said sense amplifier, and means for enabling said first transfer circuit when one of said first and third word lines is selected and enabling said second transfer circuit when one of said second and fourth word line is selected.
Claim 2
Dependent Claim
144 words
A semiconductor memory device comprising first to fourth bit lines arranged consecutively in parallel, first to fourth memory cells coupled to said first to fourth bit lines, respectively, first to fourth word lines coupled to said first to fourth memory cells, respectively, a sense amplifiers having a pair of input terminals, means for selecting one of said first to fourth word lines, a first transfer circuit for operatively connecting said first and third bit lines to said pair of input terminals of said sense amplifier, a second transfer circuit for operatively connecting said second and fourth bit lines to said pair of input terminals of said sense amplifier, and means for enabling said first transfer circuit when one of said first and third word lines is selected and enabling said second transfer circuit when one of said second and fourth word line is selected.
Claim 3
Dependent Claim
66 words
The memory device according to claim 1, in which said first transfer circuit includes a pair of first transistors coupled between said first and third bit lines and said pair of input terminals of said sense amplifier and said second transfer circuit includes a pair of second transistors coupled between said second and fourth bit lines and said pair of input terminals of said sense amplifier.
Claim 4
Dependent Claim
23 words
The memory device according to claim 1, further comprising precharge for operatively precharging said first to fourth bit lines to a predetermined potential.
Claim 5
Dependent Claim
23 words
The memory device according to claim 1, in which each of said first to fourth memory cells includes a capacitor and a transistor.
Claim 6
Dependent Claim
91 words
A semiconductor memory device comprising a plurality of bit lines arranged in parallel, a sense amplifier having first and second input terminals, first means for selectively connecting one of said bit lines to said first input terminal, second means for selectively connecting another one of said bit lines to said bit lines, said another one of said bit lines being apart from said one of said bit lines via at least one bit lines therebetween, a plurality of memory cells coupled to said bit lines, and a plurality of word lines.
Claim 7
Dependent Claim
91 words
A semiconductor memory device comprising a plurality of bit lines arranged in parallel, a sense amplifier having first and second input terminals, first means for selectively connecting one of said bit lines to said first input terminal, second means for selectively connecting another one of said bit lines to said bit lines, said another one of said bit lines being apart from said one of said bit lines via at least one bit lines therebetween, a plurality of memory cells coupled to said bit lines, and a plurality of word lines.
References Cited (Backward Citations)
No citation records indexed.
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