Abstract The fault detection signal transmission system has a transmit terminal and a receive terminal. The transmit terminal comprises a fault detector (14), a multiplex conversion circuit (13) for producing a multiplex signal by multiplexing at least a parity check signal with an output signal of the transmit interface circuit to produce a multiplexed signal, a transmit parity check circuit (16) for checking parity of the multiplexed signal, and a parity check signal output circuit (15) responsive to the fault detection signal and an output signal of the transmit parity check circuit for, when the fault detection signal is representative of a fault, producing the parity check signal by inverting a logical state of the output signal of the transmit parity check circuit. The receive terminal comprises a demultiplex conversion circuit (21) for extracting from a received signal the parity check signal, a receive parity check circuit (25) for checking parity of the received signal, and a parity check signal comparison decision circuit (26) for deciding whether or not an apparatus fault exists by comparing the parity check signal extracted by the demultiplex conversion circuit and an output signal of the receive parity check circuit. This system transmits an apparatus fault detection signal without resorting to a particular time slot and, thus, improves the transmission efficiency.
A fault detection signal transmission system having a transmit terminal and a receive terminal, said transmit terminal comprising: a fault detector circuit for generating a fault detecting signal by detecting an apparatus fault based on at least an input state of a transmit interface circuit; a multiplex conversion circuit for producing a multiplex signal by multiplexing at least a parity check signal with an output signal of said transmit interface circuit to produce a multiplexed signal; a transmit parity check circuit for checking parity of said multiplexed signal; and a parity check signal output circuit responsive to said fault detection signal and an output signal of said transmit parity check circuit for, when said fault detection signal is representative of a fault, producing said parity check signal by inverting a logical state of the output signal of said transmit parity check circuit; said receive terminal comprising: a demultiplex conversion circuit for extracting from a received signal said parity check signal which is inserted at said transmit terminal; a receive parity check circuit for checking parity of said received signal; and a parity check signal comparison decision circuit for deciding whether or not an apparatus fault exists by comparing said parity check signal extracted by said demultiplex conversion circuit and an output signal of said receive parity check circuit.
Claim 2
Dependent Claim
218 words
A fault detection signal transmission system having a transmit terminal and a receive terminal, said transmit terminal comprising: a fault detector circuit for generating a fault detecting signal by detecting an apparatus fault based on at least an input state of a transmit interface circuit; a multiplex conversion circuit for producing a multiplex signal by multiplexing at least a parity check signal with an output signal of said transmit interface circuit to produce a multiplexed signal; a transmit parity check circuit for checking parity of said multiplexed signal; and a parity check signal output circuit responsive to said fault detection signal and an output signal of said transmit parity check circuit for, when said fault detection signal is representative of a fault, producing said parity check signal by inverting a logical state of the output signal of said transmit parity check circuit; said receive terminal comprising: a demultiplex conversion circuit for extracting from a received signal said parity check signal which is inserted at said transmit terminal; a receive parity check circuit for checking parity of said received signal; and a parity check signal comparison decision circuit for deciding whether or not an apparatus fault exists by comparing said parity check signal extracted by said demultiplex conversion circuit and an output signal of said receive parity check circuit.
Claim 3
Dependent Claim
18 words
A system as claimed in claim 1, wherein said parity check signal output circuit comprises an Exclusive-OR gate.
Claim 4
Dependent Claim
21 words
A system as claimed in claim 1 or 2, wherein said parity check signal comparison decision circuit comprises an Exclusive-OR gate.
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