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EP0264215A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Fast entry to emulation

Assignee: Fujitsu IT Holdings Inc
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Filing: 1987-10-05
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Granted: —
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Expires: 2007-10-05
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Abstract

Abstract In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information - a set of locations having been preselected as address registers for implied domain addressing.

Inventors

  • 👤 Robert M. Maier
  • 👤 John C. Andoh
  • 👤 Arno S. Krakauer
  • 👤 Richard J. Tobias
  • 👤 Allan J. Zmyslowski

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 21:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 183 words
A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of_instructions in the second domain, comprising: decoding means, responsive to an instruction in the first state, for decoding the instruction to generate a control code, the control code including a branch signal and a branch test signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the second state to enter the fast program of instructions in the second domain; means, connected to receive the branch test signal, for testing for program execeptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to the alternative program of instructions.
Claim 2
Dependent Claim 183 words
A data processing apparatus operating under program control in a first state, having a first domain of facilities within the apparatus including first domain storage space, or in a second state having a second domain of facilities within the apparatus including second domain storage space, for processing a sequence of instructions normally in the first state, the sequence of instructions including an instruction that results in a branch to the second state for execution of a program of_instructions in the second domain, comprising: decoding means, responsive to an instruction in the first state, for decoding the instruction to generate a control code, the control code including a branch signal and a branch test signal; means, connected to receive and responsive to the branch signal, for branching program control of the apparatus to the second state to enter the fast program of instructions in the second domain; means, connected to receive the branch test signal, for testing for program execeptions upon a branch to the second state; and means, responsive to a program exception, for causing a branch to the alternative program of instructions.
Claim 3
Dependent Claim 40 words
The apparatus of claim 1, wherein the first state is a user state and the second state is a control state, the user state having access to domain storage space and the control state having access to system storage space.
Claim 4
Dependent Claim 22 words
The apparatus of claim 1, wherein the fast program of instructions operations to emulate execution of an instruction in the first state.
Claim 5
Dependent Claim 22 words
The apparatus of claim 1, wherein the means for testing for program exceptions includes: means for performing an operand address alignment testing.
Claim 6
Dependent Claim 35 words
The apparatus of claim 1, wherein the means for testing for program exceptions includes: means for testing whether the instruction that results in a branch to the second state is target of an execute instruction.
Claim 7
Dependent Claim 34 words
The apparatus of claim 1, wherein the means for testing for program exceptions includes: means for testing whether the instruction that results in a branch to the second state occurs during a supervisor state.

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