Compensation and biasing of wideband amplifiers

Claim 2

A wideband amplifier characterised in that it comprises first differential gain means (A1) having a noninverting input terminal for receiving a first input voltage (vni), a inverting input terminal and an output terminal; first transistor means (Qx) having a first terminal connected to the output terminal of said first differential gain means (A1), second and third terminals; second transistor means (Qy) having a first terminal connected to the output terminal of said first differential gain means (A1), second and third terminals; gain means (A(s)) connected to the third terminal of said first transistor means (Qx) and having an inverting input terminal connected to the third terminal of said second transistor means (Qy), and an output terminal comprising an output terminal of said wideband amplifier; first resistor means (Rf) connected between the output terminal of said second differential gain means (A(s)) and the second terminal of said second transistor means (Qy) to provide a feedback path therebetween; and second resistor means (Rg) connected between the second terminal of said second transistor means (Qy) and a source of a second input voltage, said second resistor means (Rg) being operative for setting the voltage gain of said wideband amplifier.

Claim 3

A wideband amplifier as claimed in claim 1, characterised in that the gain means (A(s)) is a differential gain means with a noninverting input terminal connected to the third terminal of the second transistor means (Qy).

Claim 4

A wideband amplifier as claimed in claim 1, characterised in that the gain means A(s) is connected to the third terminal of said first transistor means (Qx) via current mirror means having an input terminal connected to the third terminal of said first transistor means, and an output terminal connected to the third terminal of said second transistor means (Qy).

Claim 5

A wideband amplifier characterised in that it comprises first transistor means (Qx) having first, second, and third terminals; second transistor means (Qy) having corresponding first, second and third terminals; third transistor means (Qw) having corresponding first, second, and third terminals, the first terminal being connected to receive a first input voltage (vni) and the second terminal being connected to the first terminals of said first and second transistor means (Qx,Qy); fourth transistor means (Qxa) having corresponding first, second, and third terminals, the second terminal being connected to the second terminal of said first transistor means (Qx); fifth transistor means (Qya) having corresponding first, second, and third terminals, the second terminal being connected to the second terminal of said second transistor means (Qy); sixth transistor means (Qwa) having corresponding first, second, and third terminals, the first terminal being connected to the first terminal of said third transistor means (Qw) and to receive said first input voltage (vni) and the second terminal being connected to the first terminals of said fourth and fifth transistor means (Qxa, Qya); first current bias means connected between the second terminal of said sixth transistor means (Qwa) and a first supply voltage (+Vcc); second current bias means connected between the second terminal of said third transistor means (Qw) and a second supply voltage (-Vcc); gain means (A(s), xn) having an input terminal connected to the third terminal of said second transistor means (Qy), said gain means (A(s), xn) also having an output terminal comprising an output terminal of said wideband amplifier; first resistor means (Rf) connected between the output terminal of said gain means (A(s) and the second terminal of said second transistor means (Qy) to provide a feedback path therebetween; and second resistor means (Rg) connected between the second terminal of said second transistor means (Qy) and a source of a second input voltage, said second resistor means (Rg) being operative for setting the voltage gain of said wideband amplifier.

Claim 6

A wideband amplifier characterised in that it comprises first transistor means (Qx) having first, second, and third terminals; second transistor means (Qy) having corresponding first, second and third terminals; third transistor means (Qw) having corresponding first, second, and third terminals, the first terminal being connected to receive a first input voltage (vni) and the second terminal being connected to the first terminals of said first and second transistor means (Qx,Qy); fourth transistor means (Qxa) having corresponding first, second, and third terminals, the second terminal being connected to the second terminal of said first transistor means (Qx); fifth transistor means (Qya) having corresponding first, second, and third terminals, the second terminal being connected to the second terminal of said second transistor means (Qy); sixth transistor means (Qwa) having corresponding first, second, and third terminals, the first terminal being connected to the first terminal of said third transistor means (Qw) and to receive said first input voltage (vni) and the second terminal being connected to the first terminals of said fourth and fifth transistor means (Qxa, Qya); first current bias means connected between the second terminal of said sixth transistor means (Qwa) and a first supply voltage (+Vcc); second current bias means connected between the second terminal of said third transistor means (Qw) and a second supply voltage (-Vcc); gain means (A(s), xn) having an input terminal connected to the third terminal of said second transistor means (Qy), said gain means (A(s), xn) also having an output terminal comprising an output terminal of said wideband amplifier; first resistor means (Rf) connected between the output terminal of said gain means (A(s) and the second terminal of said second transistor means (Qy) to provide a feedback path therebetween; and second resistor means (Rg) connected between the second terminal of said second transistor means (Qy) and a source of a second input voltage, said second resistor means (Rg) being operative for setting the voltage gain of said wideband amplifier.

Claim 7

A wideband amplifier as claimed in claim 4, characterised in that the gain means (A(s)) is a differential gain means said input terminal connected to the third terminal of the second transistor means (Qy) being an inverting terminal, the noninverting input terminal being connected to the third terminal of said first transistor means (Qx).

Claim 8

A wideband amplifier as claimed in claim 4, characterised in that it further comprises current mirror means having an input terminal connected to the third terminal of said first transistor means (Qx) and having an output terminal connected to the third terminal of said second transistor means (Qy), and said gain means is an inverting gain means (-A(s)).

Claim 9

A wideband amplifier as claimed in claim 4, characterised in that it further comprises first current mirror means having an input terminal connected to the third terminal of said first transistor means (Qx) and having an output terminal connected to the third terminal of said second transistor means (Qy); seventh transistor means (Qs) having corresponding first, second, and third terminals, the first terminal being connected to the third terminal of said second transistor means (Qy); and second current mirror means having an input terminal connected to the third terminal of said fourth transistor means (Qxa) and having an output terminal connected to the third terminal of said seventh transistor means (Qs); said gain means being a noninverting gain means (xn) having its input terminal connected to the third terminal of the second transistor means (Qy) via the first and third terminals of said seventh transistor means (Qs).

Claim 10

A wideband amplifier as claimed in claim 7, wherein the input terminal of said second current mirror means is also connected to the third terminal of the fifth transistor means (Qya).

Claim 11

A feedback amplifier characterised in that it comprises input buffer amplifier means (A1,Qx,Qy;Qx,Qy,Qw,Qxa,Qya,Qwa) having an input terminal for receiving a first input signal (vni) and having first and second buffer output terminals (node x, node y), said input buffer amplifier means being operative for controlling a voltage signal at the first buffer output terminal in common with a voltage signal at the second buffer output terminal and for providing a buffer output voltage signal that is common to both of said first and second buffer output terminals, said input buffer amplifier means being further operative for controlling the buffer output voltage signal in accordance with the first input signal, while allowing currents to flow independently of each other to or from said first and second buffer output terminals, said input buffer amplifier means being further operative for providing a current sense signal that is responsive to the algebraic difference between the currents flowing to or from said first and second buffer output terminals; output amplifier means (A(s)) having an output comprising an output terminal of said feedback amplifier for controlling a voltage signal at said output terminal in accordance with said current sense signal while allowing a current to flow to or from said output terminal; current feedback means (Rf) connected between said output terminal and said first buffer output terminal (node y) for causing a current to flow into said first buffer output terminal that is responsive to the algebraic difference between the voltage signal at said output terminal and the buffer output voltage signal; and gain setting means (Rg) connected between a source of a second input signal and said first buffer output terminal (node y) for causing an additional current to flow into said first buffer output terminal, said additional current being responsive to the algebraic difference between said second input signal and said buffer output voltage signal.

Claim 12

A feedback amplifier characterised in that it comprises input buffer amplifier means (A1,Qx,Qy;Qx,Qy,Qw,Qxa,Qya,Qwa) having an input terminal for receiving a first input signal (vni) and having first and second buffer output terminals (node x, node y), said input buffer amplifier means being operative for controlling a voltage signal at the first buffer output terminal in common with a voltage signal at the second buffer output terminal and for providing a buffer output voltage signal that is common to both of said first and second buffer output terminals, said input buffer amplifier means being further operative for controlling the buffer output voltage signal in accordance with the first input signal, while allowing currents to flow independently of each other to or from said first and second buffer output terminals, said input buffer amplifier means being further operative for providing a current sense signal that is responsive to the algebraic difference between the currents flowing to or from said first and second buffer output terminals; output amplifier means (A(s)) having an output comprising an output terminal of said feedback amplifier for controlling a voltage signal at said output terminal in accordance with said current sense signal while allowing a current to flow to or from said output terminal; current feedback means (Rf) connected between said output terminal and said first buffer output terminal (node y) for causing a current to flow into said first buffer output terminal that is responsive to the algebraic difference between the voltage signal at said output terminal and the buffer output voltage signal; and gain setting means (Rg) connected between a source of a second input signal and said first buffer output terminal (node y) for causing an additional current to flow into said first buffer output terminal, said additional current being responsive to the algebraic difference between said second input signal and said buffer output voltage signal.

Claim 13

A feedback amplifier as in claim 9, characterised in that it further comprises first and second current sense terminals and wherein: said input buffer amplifier means and said output amplifier means (A(s)) are coupled to said first and second current sense terminals; said input buffer amplifier means is further operative for controlling first and second sense currents flowing into said first and second current sense terminals such that the algebraic difference between said first and second sense currents is responsive to the algebraic difference between said currents flowing independently of each other to and from said first and second buffer output terminals; and said current sense signal is equal to the algebraic difference between said first and second sense currents flowing into said first and second current sense terminals.