Concurrent memory access system

Claim 3

The system according to claim 1 wherein said memory management means comprises: port means for communicating with said data processing devices for providing a memory bank address for each memory bank access by each data processing device, and for generating indicating signals indicating which of said memory banks each data processing device is to access; a plurality of address multiplexing means, each corresponding to a separate one of said memory banks, and each for providing an address for accessing the corresponding memory bank, the address being selected from among said addresses provided by said port means; a plurality of data multiplexing means, each corresponding to a separate one of said memory banks, and each for completing a data path between the corresponding memory bank and any selected one of said data processing devices; and controller means for generating control signals for controlling the operation of each memory bank during each memory bank access and for controlling each address multiplexing means and each data multiplexing means according to said indicating signals generated by said port means.

Claim 4

The system according to claim 2 wherein said controller means comprises arbitration means responsive to said indicating signals for determining which of said data processing devices is to access each memory bank at any given time.

Claim 5

The system according to claim 2 wherein said port means includes a sequential address generator for generating a sequence of said memory bank addresses, said sequential address generator comprising: means for storing a base address; means for maintaining a count of the number of times said memory banks are addressed by a memory address of said sequence of memory bank addresses; and means for adding said base address to said count to generate each memory bank address of said sequence of memory bank addresses.

Claim 6

A digital oscilloscope comprising: a plurality of independently accessable memory banks, each memory bank for providing a separate portion of an addressable memory space digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space; processing means for generating a sequence of processed waveform data to be stored in said addressable memory space; and memory management means for providing access to any one of said memory banks for said digitizer means while providing concurrent access to any other of said memory banks for said processing means.

Claim 7

A digital oscilloscope comprising: a plurality of independently accessable memory banks, each memory bank for providing a separate portion of an addressable memory space digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space; processing means for generating a sequence of processed waveform data to be stored in said addressable memory space; and memory management means for providing access to any one of said memory banks for said digitizer means while providing concurrent access to any other of said memory banks for said processing means.

Claim 8

A digital oscilloscope comprising: a plurality of independently accessable memory banks, each memory bank for providing a separate portion of an addressable memory space digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space; a screen for displaying waveform images; display controller means for displaying waveform images on said screen based on sampled waveform data sequences stored in said addressable memory space on said screen; and memory management means for providing access to one of said memory banks for one of said digitizer and display controller means while providing concurrent access to any other of said memory banks for the other of said digitizer and display controller means.

Claim 9

A digital oscilloscope comprising: a plurality of independently accessable memory banks, each memory bank for providing a separate portion of an addressable memory space digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space; a screen for displaying waveform images; display controller means for displaying waveform images on said screen based on sampled waveform data sequences stored in said addressable memory space on said screen; and memory management means for providing access to one of said memory banks for one of said digitizer and display controller means while providing concurrent access to any other of said memory banks for the other of said digitizer and display controller means.

Claim 10

The digital oscillosope according to claim 6 wherein said memory management means comprises: port means for communicating with said digitizer and display controller means, for providing a memory bank address for each memory bank access by each of said digitizer and display controller means, and for generating indicating signals indicating which of said memory banks each of said digitizer and display controller means is to access; a plurality of address multiplexing means, each corresponding to a separate one of said memory banks, and each for providing an address for accessing the corresponding memory bank, the address being selected from among said addresses provided by said port means; a plurality of data multiplexing means, each corresponding to a separate one of said memory banks, and each for completing a data path between the corresponding memory bank and any selected one of said digitizer and display controller means; and controller means for generating control signals for controlling the operation of each memory bank during each memory bank access and for controlling each address multiplexing means and each data multiplexing means according to said indicating signals generated by said port means.

Claim 11

The digital oscilloscope according to claim 7 wherein said port means includes a sequential address generator for generating a sequence of said memory bank addresses, said sequential address generator comprising: means for storing a base address; means for maintaining a count of the number of times said memory banks are addressed by a memory address of said sequence of memory bank addresses; and means for adding said base address to said count to generate each memory bank address of said sequence of memory bank addresses.