Patent EP0261685A2 successfully refreshed from Google Patents.
EP0261685A2
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Microprocessor system
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1987-09-24
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Granted: —
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Expires: 2007-09-24
Abstract
Abstract When the coprocessor communicates a plurality of data items with the master processor and the memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with an information indicating a data storage position as a data transfer source or destination, and the master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto and further is not required to indicate the end of the sequence of data transfer cycles to the master processor.
Inventors
- 👤 Kouzi Hashimoto
- 👤 Atsushi Hasegawa
- 👤 Ikuya Kawasaki
- 👤 Kazuhiko Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
77 words
A microprocessor system comprising: a coprocessor (2) and a master processor (1) for executing a bus access cycle for said coprocessor (20; said coprocessor (2) including first judge means (34) for judging a completion of a sequence of data transfer operations effected between an internal section of the coprocessor and an external device with respect thereto and said master processor (1) including second judge means (29) for judging a completion of said sequence of data transfer operations.
Claim 2
Dependent Claim
77 words
A microprocessor system comprising: a coprocessor (2) and a master processor (1) for executing a bus access cycle for said coprocessor (20; said coprocessor (2) including first judge means (34) for judging a completion of a sequence of data transfer operations effected between an internal section of the coprocessor and an external device with respect thereto and said master processor (1) including second judge means (29) for judging a completion of said sequence of data transfer operations.
Claim 3
Dependent Claim
24 words
A microprocessor system according to claim 1 wherein said second judge means effect a judgement based on a count of the data transfer operations.
Claim 4
Dependent Claim
108 words
A microprocessor system according to claim 2 wherein said first judge means (34) and said second judge means (29) each are find first one circuits respectively disposed in the coprocessor and the master processor, said each fine first one circuit effecting for each data transfer a code inversion in a bit-by-bit fashion on a predetermined code bit included in an information of a plurality of bits set to said each find first one circuit so as to update the information and effecting a judgement of a completion of operations for the data transfer based on a condition that the updated information does not include the predetermined code bit.
Claim 5
Dependent Claim
40 words
A microprocessor system according to claim 3 wherein said information of the plurality of bits designates, based on a combination of each bit code, a predetermined one of a plurality of internal data storage means (15) possessed by the coprocessor.
Claim 6
Dependent Claim
33 words
A microprocessor system according to claim 4 wherein said find first one circuit decodes an information of a plurality of bits set thereto, thereby controlling a designation of said internal data storage means.
Claim 7
Dependent Claim
30 words
A microprocessor system according to claim 5 wherein said information of the plurality of bits is contained in an instruction to be fetched by the master processor for the coprocessor.
Claim 8
Dependent Claim
46 words
A microprocessor system according to claim 6 wherein said master processor includes a step for slicing an instruction to be fetched by the master processor for the coprocessor and for generating a command for the coprocessor, said command containing the information of said plurality of bits.
Claim 9
Dependent Claim
22 words
A microprocessor system according to claim 4 wherein said plurality of internal data storage means include a plurality of general-purpose registers (32).
Claim 10
Dependent Claim
187 words
A microprocessor system includes steps for an operation effected by a coprocessor (2) to communicate a sequence of plural data between an external device and a plurality of data storage means included therein according to a bus access cycle activated by a master processor (1), said steps including: a step to be used by the master processor to fetch an instruction for the coprocessor; a step to be used by the master processor to generate a command for the coprocessor based on the instruction fetched in the fetch step; and a step to be used by the master processor to supply the command generated in the step to the coprocessor, said instruction and said command each including information indicating a data storage location as a data transfer source or a data transfer destination in the coprocessor, said master processor futher including a step for monitoring an end of a sequence of data transfer operations based on the information contained in the instruction, and said coprocessor including a step for monitoring an end of a sequence of data transfer operations based on the information contained in the command.
Claim 11
Dependent Claim
187 words
A microprocessor system includes steps for an operation effected by a coprocessor (2) to communicate a sequence of plural data between an external device and a plurality of data storage means included therein according to a bus access cycle activated by a master processor (1), said steps including: a step to be used by the master processor to fetch an instruction for the coprocessor; a step to be used by the master processor to generate a command for the coprocessor based on the instruction fetched in the fetch step; and a step to be used by the master processor to supply the command generated in the step to the coprocessor, said instruction and said command each including information indicating a data storage location as a data transfer source or a data transfer destination in the coprocessor, said master processor futher including a step for monitoring an end of a sequence of data transfer operations based on the information contained in the instruction, and said coprocessor including a step for monitoring an end of a sequence of data transfer operations based on the information contained in the command.
Claim 12
Dependent Claim
45 words
A microprocessor according to claim 9 wherein the monitor step to be effected by the master processor includes a step operative after a detection of the end of the sequence of data transfer operations for stopping an activation of a bus access cycle subsequent thereto.
Claim 13
Dependent Claim
43 words
A microprocessor according to claim 9 or 10 wherein the monitor step by the coprocessor includes a step operative after a detection of the end of the sequence of data transfer operations for stopping an input or output operation of data subsequent thereto.
Claim 14
Dependent Claim
44 words
A microprocessor according to claim 9 further including a step operative based on the information contained in the command for judging and for designating for each data transfer cycle a data storage position used as a data transfer source or destination in the coprocessor.
Claim 15
Dependent Claim
104 words
A microprocessor according to claim 12 wherein said step for judging and for designating for each data transfer cycle a data storage position is effected by a find first one circuit, said find first one circuit effecting for each data transfer a code inversion in a bit-by-bit fashion on a predetermined code bit included in an information of a plurality of bits set to said each fine first one circuit so as to update the information and effecting a judgement of a completion of operations for the data transfer based on a condition that the updated information does not include the predetermined code bit.
Claim 16
Dependent Claim
39 words
A microprocessor system according to claim 13 wherein said information of the plurality of bits designates, based on a combination of each bit code, a predetermined one of a plurality of internal data storage means possessed by the coprocessor.
References Cited (Backward Citations)
No citation records indexed.
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