Patent EP0260568A2 successfully refreshed from Google Patents.
EP0260568A2
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EP
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Computer systems speed control at continuous processor speed
Assignee: Compaq Computer Corp
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Filing: 1987-09-07
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Granted: —
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Expires: 2007-09-07
Abstract
Abstract A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to the speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. The "STOP" state of the microprocessor is varied by varying the time delay setting of a one-shot timer. The one-shot timer keeps the "STOP" request active and therefore keeps the microprocessor (CPU) from running bus cycles (executting code) until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, which halts the execution of bus cycles (code), the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computer with older microprocessors. The computer and software disclosed enhances compatability of a faster microprocessor with older applications programs written for slower microprocessor without varying the microprocessor clock rate.
Inventors
- 👤 Paul R. Culley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 03:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
103 words
A personal computer with a high speed microprocessor compatible with applications software written for slower speed microprocessors characterized by: a) a high speed microprocessor; b) a dynamic memory; c) a read only memory; d) a timing device to set the clock rate of the microprocessor; e) means responsive to a mode select signal to place the execution of bus cycles on hold for a pre-determined time period; f) a program storage device; and g) logic means to generate mode select signal for controlling the length of the hold state of the high speed microprocessor to simulate a slower operating speed of said microprocessor.
Claim 2
Dependent Claim
103 words
A personal computer with a high speed microprocessor compatible with applications software written for slower speed microprocessors characterized by: a) a high speed microprocessor; b) a dynamic memory; c) a read only memory; d) a timing device to set the clock rate of the microprocessor; e) means responsive to a mode select signal to place the execution of bus cycles on hold for a pre-determined time period; f) a program storage device; and g) logic means to generate mode select signal for controlling the length of the hold state of the high speed microprocessor to simulate a slower operating speed of said microprocessor.
Claim 3
Dependent Claim
41 words
The personal computer described in claim 1 further characterized by logic means monitoring a floppy diskette program storage device to initiate a slow down of the microprocessor speed by specifying a value for the pre-determined length of the microprocessor hold state.
Claim 4
Dependent Claim
16 words
The personal computer described in claim 1 characterized in that the microprocessor is a 32-bit microprocessor.
Claim 5
Dependent Claim
32 words
The personal computer described in claim 1 characterized in that the logic means includes pre-determined values for the different lengths of the hold states to simulate operating speeds of older generation microprocessors.
Claim 6
Dependent Claim
113 words
A personal computer system characterized by: a) a microprocessor operatively coupled to the following: i) at least one input/output device, ii) a timing device to set the clock rate of the microprocessor, iii) a dynamic memory to store date transfers to and from the microprocessor, iv) means to halt the execution of bus cycles of said microprocessor for a pre-set time interval, v) a keyboard; b) an operating system; c) means for varying the pre-set time that the execution of bus cycles is placed on hold; d) means to initiate the execution of the hold for said pre-set time; e) means to re-intiate the execution of bus cycles after completion of the hold.
Claim 7
Dependent Claim
113 words
A personal computer system characterized by: a) a microprocessor operatively coupled to the following: i) at least one input/output device, ii) a timing device to set the clock rate of the microprocessor, iii) a dynamic memory to store date transfers to and from the microprocessor, iv) means to halt the execution of bus cycles of said microprocessor for a pre-set time interval, v) a keyboard; b) an operating system; c) means for varying the pre-set time that the execution of bus cycles is placed on hold; d) means to initiate the execution of the hold for said pre-set time; e) means to re-intiate the execution of bus cycles after completion of the hold.
Claim 8
Dependent Claim
37 words
The personal computer set forth in Claim 5 characterized in that the pre-set time interval is a fixed time and the execution of the pre-set time hold is initiated by monitoring the use of the input/output device.
Claim 9
Dependent Claim
111 words
A personal computer system with varying execution speeds,characterized by: a) a microprocessor operatively coupled to the following: i) at least one input/output device, ii) a timing device to set the clock rate of the microprocessor, iii) a memory device to store data transfers to and from the microprocessor, iv) means to place the execution of bus cycles of said microprocessor on hold for a pre-set time, v) means to re-initiate the execution of bus cycles after completion of the hold for said pre-set time, vi) a keyboard, and b) an operating system; wherein the microprocessor operates at a simulated reduction in operating speed while the timing device clock rate remains constant.
Claim 10
Dependent Claim
111 words
A personal computer system with varying execution speeds,characterized by: a) a microprocessor operatively coupled to the following: i) at least one input/output device, ii) a timing device to set the clock rate of the microprocessor, iii) a memory device to store data transfers to and from the microprocessor, iv) means to place the execution of bus cycles of said microprocessor on hold for a pre-set time, v) means to re-initiate the execution of bus cycles after completion of the hold for said pre-set time, vi) a keyboard, and b) an operating system; wherein the microprocessor operates at a simulated reduction in operating speed while the timing device clock rate remains constant.
Claim 11
Dependent Claim
28 words
A personal computer system as set forth in claim 7 characterized in that the. pre-set time is determined by monitoring the use of a floppy diskette drive motor.
Claim 12
Dependent Claim
3 words
INDEX OF APPENDICIES
Claim 13
Dependent Claim
3 words
INDEX OF APPENDICIES
Claim 14
Dependent Claim
111 words
Appendix A Mother Board Schematics B Memory Board Schematics C Mother Board Bill of Materials D DRAM Board Bill of Materials E Table I - Bus Conversion From CPU Lines to Address Lines F Table II - CPU Command/Cycle Types G Table III - Latch Disable Delay Time H Table IV - State Sequences for Typical Cycles I Table V - Non Processor Subsystem J I/O Subsystems K Interrupt Controller L ROM Memory System M Miscellaneous N KSUBS Source Code O Timer Source Code P PAL 16L8B Listing Q . PAL Design Data R TESTHRAM Source Code S Dual Mapped ROM Subroutine T Technical Reference Manual - Chapters 2 and 3
Claim 15
Dependent Claim
111 words
Appendix A Mother Board Schematics B Memory Board Schematics C Mother Board Bill of Materials D DRAM Board Bill of Materials E Table I - Bus Conversion From CPU Lines to Address Lines F Table II - CPU Command/Cycle Types G Table III - Latch Disable Delay Time H Table IV - State Sequences for Typical Cycles I Table V - Non Processor Subsystem J I/O Subsystems K Interrupt Controller L ROM Memory System M Miscellaneous N KSUBS Source Code O Timer Source Code P PAL 16L8B Listing Q . PAL Design Data R TESTHRAM Source Code S Dual Mapped ROM Subroutine T Technical Reference Manual - Chapters 2 and 3
References Cited (Backward Citations)
No citation records indexed.
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