Patent EP0259631A2 successfully refreshed from Google Patents.
EP0259631A2
Expired / Lapsed
EP
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Semiconductor device having power supply lines
Assignee: Fujitsu Ltd
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Filing: 1987-08-11
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Granted: —
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Expires: 2007-08-11
Abstract
Abstract A semiconductor device comprises a semiconductor chip (2l) having main power supply lines (23, 24, 26, 27) which are arranged in peripheral regions in the vicitity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layers (23a, 27a; 24a, 26a) of the same potential face each other through an insulating layer in chip corner regions (2la) adjacent to corners of the semiconductor chip.
Inventors
- 👤 Takehide Shirato
- 👤 Teruo Tazunoki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W74/00; H10W74/40; H10W74/47; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
102 words
A semiconductor device comprising; a semiconductor chip (2l) having main power supply lines (23, 24, 26, 27) which are arranged in peripheral regions in the vicinity of edges of said semiconductor chip, said main power lines being formed with layers of multi-levels between which an insulating layer (25) is interposed, each of said main power lines being formed with arrangements in that layers (23a, 27a; 24a, 26a) of the same potential face each other through said insulating layer in chip corner regions (2la) adjacent to corners of said semiconductor chip; and a package (l5) made of plastics for sealing said semiconductor chip.
Claim 2
Dependent Claim
102 words
A semiconductor device comprising; a semiconductor chip (2l) having main power supply lines (23, 24, 26, 27) which are arranged in peripheral regions in the vicinity of edges of said semiconductor chip, said main power lines being formed with layers of multi-levels between which an insulating layer (25) is interposed, each of said main power lines being formed with arrangements in that layers (23a, 27a; 24a, 26a) of the same potential face each other through said insulating layer in chip corner regions (2la) adjacent to corners of said semiconductor chip; and a package (l5) made of plastics for sealing said semiconductor chip.
Claim 3
Dependent Claim
53 words
A semiconductor device as claimed in claim l, characterized in that said layers of the same potential in said chip corner regions are electrically connected by means of metallic material which is filled into through holes (28a, 28b) formed in said insulating layer which is sandwiched between said layers of the same potential.
Claim 4
Dependent Claim
47 words
A semiconductor device as claimed in claim l or 2, characterized in that said layers (23a, 27a; 24a, 26a) of the same potential formed in said chip corner regions are narrower than other parts (23, 27; 24, 26) thereof in regions other than said chip corner regions.
Claim 5
Dependent Claim
47 words
A semiconductor device as claimed in any of claims l to 3, characterized in that in regions other than said chip corner regions, said main power supply lines are formed with arrangements in that layers (46, 47) of different potential face each other through said insulating layer.
Claim 6
Dependent Claim
37 words
A semiconductor device as claimed in any of claims l to 4, characterized in that said main power supply lines are formed to be concentric in peripheral regions in the vicinity of edges of said semiconductor chip.
References Cited (Backward Citations)
No citation records indexed.
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