Patent EP0259050A2 successfully refreshed from Google Patents.
EP0259050A2
Expired / Lapsed
EP
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Multi-channel memory access circuit
Assignee: AT&T Inc
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Filing: 1987-08-18
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Granted: —
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Expires: 2007-08-18
Abstract
Abstract In may situations, contiguous data is not stored at contiguous locations within a memory. This fact alone causes an increase in processor time for retrieval purposes or the intervention of a memory management unit of some type. The situation is compounded when large amounts of data must be obtained from the memory or stored in the memory in real time. This problem is addressed by arranging a dual ported memory between the main memory (11) and the processor (10) and transferring the desired data into the dual ported memory. A pair of buffers (block0, block1) in the dual ported memory is then used for each channel having access to the memory. While one buffer is being read, the other is being loaded. This structure also allows multiple devices to access the single main memory substantially simultaneously. [FIG. 1]
Inventors
- 👤 Kevin Jyo Oye
- 👤 Enzo Paterno
- 👤 Thomas Lloyd Smith
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 17:28
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1673
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
242 words
A circuit for removing data from memory for concurrent delivery to a plurality of output channels, said memory having locations therein for the storage of said data, said locations being divided into addressable bytes CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said output channels with said periodic control intervals means responsive to requests for data for delivery to a particular output channel for addressing certain of said bytes of data in said memory during said control interval uniquely associated with said particular output channel, means operative during each said control interval for removing m+1 bytes of data from said memory, said m+1 bytes consisting of a data byte from an addressed data storage area within said memory plus data bytes from m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said output channels and with said control interval associated with said particular output channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said memory to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data stored in each said buffer memory segment to said associated output channel.
Claim 2
Dependent Claim
242 words
A circuit for removing data from memory for concurrent delivery to a plurality of output channels, said memory having locations therein for the storage of said data, said locations being divided into addressable bytes CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said output channels with said periodic control intervals means responsive to requests for data for delivery to a particular output channel for addressing certain of said bytes of data in said memory during said control interval uniquely associated with said particular output channel, means operative during each said control interval for removing m+1 bytes of data from said memory, said m+1 bytes consisting of a data byte from an addressed data storage area within said memory plus data bytes from m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said output channels and with said control interval associated with said particular output channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said memory to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data stored in each said buffer memory segment to said associated output channel.
Claim 3
Dependent Claim
72 words
The circuit set forth in claim 1, CHARACTERISED IN THAT said buffer memory is arranged with a pair of segments associated with each said control interval, and wherein data which is transferred from said memory is stored alternately in said paired segments, and means for transferring data from a first one of said paired segments to an output channel while data is being transferred into the other one of said paired segments.
Claim 4
Dependent Claim
24 words
The circuit set forth in claim 1, CHARACTERISED IN THAT said addressing means is operative to address data bytes in each said control interval.
Claim 5
Dependent Claim
25 words
The circuit set forth in claim 1, CHARACTERISED IN THAT said storing means and said means for transferring data to said output channels operate concurrently.
Claim 6
Dependent Claim
46 words
The circuit set forth in claim 4, CHARACTERISED IN THAT said buffer memory includes a dual-ported memory and wherein one of said ports is arranged to receive data for storage therein and the other of said ports is arranged to transfer data to said output channels.
Claim 7
Dependent Claim
73 words
The circuit set forth in claim 1, CHARACTERISED IN THAT said data bytes are stored within said memory in units, each unit having m+1 data bytes and each unit having a starting address and wherein a plurality of said units are required to make up a message for delivery to a reading device, said memory arranged such that all of said addresses of said units of any one message are not necessarily contiguous.
Claim 8
Dependent Claim
100 words
The circuit set forth in claim 6 further CHARACTERISED BY means for dividing said control intervals into frames, each frame having n said control intervals, where n equals the number of reading devices accessible to retrieve data from said memory concurrently, and wherein said circuit further includes a processor for controlling interactions between said reading devices and said memory, said processor operable to transform a request for data for delivery to a particular reading device into a plurality of unit addresses each said address provided to said memory during the same relative control interval in subsequent ones of said frames.
Claim 9
Dependent Claim
32 words
The circuit set forth in claim 1, CHARACTERISED IN THAT data bytes stored within said memory for subsequent delivery to a particular output channel need not be stored at contiguous address locations.
Claim 10
Dependent Claim
36 words
The circuit set forth in claim 1, CHARACTERISED IN THAT said memory to buffer memory transferring and storing means includes means for storing the same data bytes in a plurality of segments within said buffer memory.
Claim 11
Dependent Claim
17 words
The circuit set forth in claim 1, CHARACTERISED IN THAT n equals the number of output channels.
Claim 12
Independent Claim
269 words
A system for retrieving data messages from a memory in which each such message is sub-divided into blocks, each block having m bytes of data stored in said memory at contiguous locations therein, each data block also having a starting address, CHARACTERISED IN THAT such starting addresses for a particular data message need not be at contiguous or predefined locations within said memory, and in that said system comprises means for supplying retrieved messages concurrently to a plurality n of output channels, means for assembling said starting addresses for each said message block to be delivered to any said channel at a particular time, means for generating frames of control intervals, each such frame containing n such control intervals, each such control interval in repetitive ones of said frames associated with one of said n output channels, means operative during each repetitive control interval associated with a particular output channel for providing to said memory any assembled ones of said addresses for said particular output channel, a buffer divided into n segment, each segment associable with a particular one of said output channels and with said control interval associated with said particular output channels, each said segment having storage capability for a block of said data from said memory, means responsive to said providing means and operable during each said control interval for storing a block of data from said memory in said buffer in said segment of said buffer associated with said control interval, and means responsive to each said control interval for transferring data stored in said buffer to said output channel associated with said control interval.
Claim 13
Independent Claim
269 words
A system for retrieving data messages from a memory in which each such message is sub-divided into blocks, each block having m bytes of data stored in said memory at contiguous locations therein, each data block also having a starting address, CHARACTERISED IN THAT such starting addresses for a particular data message need not be at contiguous or predefined locations within said memory, and in that said system comprises means for supplying retrieved messages concurrently to a plurality n of output channels, means for assembling said starting addresses for each said message block to be delivered to any said channel at a particular time, means for generating frames of control intervals, each such frame containing n such control intervals, each such control interval in repetitive ones of said frames associated with one of said n output channels, means operative during each repetitive control interval associated with a particular output channel for providing to said memory any assembled ones of said addresses for said particular output channel, a buffer divided into n segment, each segment associable with a particular one of said output channels and with said control interval associated with said particular output channels, each said segment having storage capability for a block of said data from said memory, means responsive to said providing means and operable during each said control interval for storing a block of data from said memory in said buffer in said segment of said buffer associated with said control interval, and means responsive to each said control interval for transferring data stored in said buffer to said output channel associated with said control interval.
Claim 14
Dependent Claim
72 words
The system set forth in claim 11, CHARACTERISED IN THAT said buffer memory is arranged with a pair of segments associated with each said control interval and wherein data which is transferred from said memory is stored alternately in said paired segments, and means for transferring data from a first one of said paired segments to an output channel while data is being transferred into the other one of said paired segments.
Claim 15
Independent Claim
293 words
A system for retrieving data messages from, or storing messages in, a memory in which each such message is sub-divided into blocks, each block having m bytes of data stored in said memory at contiguous locations therein, each data block also having a starting address CHARACTERISED IN THAT such starting addresses for a particular data message need not be at contiguous or predefined locations within said memory, and in that said system comprises means for supplying retrieved messages concurrently to, or for receiving messages concurrently from, a plurality of n channels, means for assembling said starting addresses for each said message block to be delivered to or received from any said channel at a particular time, means for generating frames of control intervals, each such frame containing n such control intervals, each such control interval in repetitive ones of said frames associated with one of said n channels, means operative during each repetitive control interval associated with a particular channel for providing to said memory any assembled ones of said addresses for said particular channel, a buffer divided into n segments each segment associable with a particular one of said channels and with said control interval associated with said particular channels, each said segment having storage capability for a block of said data stored or retrieved from said memory, means responsive to said providing means and operable during each said control interval for storing or retrieving a block of data from said memory in said buffer in said segment of said buffer associated with said control interval, and means responsive to each said control interval for transferring data from said buffer to said channel associated with said control interval or transferring data from said channel associated with said control interval to said buffer.
Claim 16
Independent Claim
293 words
A system for retrieving data messages from, or storing messages in, a memory in which each such message is sub-divided into blocks, each block having m bytes of data stored in said memory at contiguous locations therein, each data block also having a starting address CHARACTERISED IN THAT such starting addresses for a particular data message need not be at contiguous or predefined locations within said memory, and in that said system comprises means for supplying retrieved messages concurrently to, or for receiving messages concurrently from, a plurality of n channels, means for assembling said starting addresses for each said message block to be delivered to or received from any said channel at a particular time, means for generating frames of control intervals, each such frame containing n such control intervals, each such control interval in repetitive ones of said frames associated with one of said n channels, means operative during each repetitive control interval associated with a particular channel for providing to said memory any assembled ones of said addresses for said particular channel, a buffer divided into n segments each segment associable with a particular one of said channels and with said control interval associated with said particular channels, each said segment having storage capability for a block of said data stored or retrieved from said memory, means responsive to said providing means and operable during each said control interval for storing or retrieving a block of data from said memory in said buffer in said segment of said buffer associated with said control interval, and means responsive to each said control interval for transferring data from said buffer to said channel associated with said control interval or transferring data from said channel associated with said control interval to said buffer.
Claim 17
Dependent Claim
106 words
The system set forth in claim 11, CHARACTERISED IN THAT said buffer memory is arranged with a pair of segments associated with each said control interval and wherein data which is transferred to or from said memory is stored alternately in said paired segments, and means for transferring data from a first one of said paired segments to said channel while data is being transferred into the other one of said paired segments from memory or for transferring data to a first one of said paired segments from said channel while data is being transferred out of the other one of said paired segments into memory.
Claim 18
Dependent Claim
279 words
A circuit for handling data to or from memory for concurrent delivery from or to a plurality of channels, said memory having locations therein for the storage of said data, said locations being divided into addressable byte locations, CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said channels with said periodic control intervals, means responsive to requests for data for delivery from or to a particular channel for addressing certain of said byte locations in said memory during said control interval uniquely associated with said particular channel, means operative during each said control interval for removing m+1 bytes of data from said memory or from said channels, said m+1 bytes consisting of a data byte associated with an addressed data storage area within said memory plus data bytes associated with m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said channels and with said control interval associated with said particular channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said memory or from said channels to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data which is stored in each said buffer memory segment from said memory to said associated channel or for sequentially transferring data which is stored in each said buffer memory segment from said channels to said associated memory byte locations.
Claim 19
Dependent Claim
279 words
A circuit for handling data to or from memory for concurrent delivery from or to a plurality of channels, said memory having locations therein for the storage of said data, said locations being divided into addressable byte locations, CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said channels with said periodic control intervals, means responsive to requests for data for delivery from or to a particular channel for addressing certain of said byte locations in said memory during said control interval uniquely associated with said particular channel, means operative during each said control interval for removing m+1 bytes of data from said memory or from said channels, said m+1 bytes consisting of a data byte associated with an addressed data storage area within said memory plus data bytes associated with m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said channels and with said control interval associated with said particular channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said memory or from said channels to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data which is stored in each said buffer memory segment from said memory to said associated channel or for sequentially transferring data which is stored in each said buffer memory segment from said channels to said associated memory byte locations.
Claim 20
Dependent Claim
69 words
The circuit set forth in claim 15, CHARACTERISED IN THAT said buffer memory is arranged with a pair of segments associated with each said control interval and wherein data which is transferred to said buffer memory is stored alternately in said paired segments, and means for transferring data from a first one of said paired segments while data is being transferred into the other one of said paired segments.
Claim 21
Dependent Claim
273 words
A circuit for removing data from an input channel for concurrent delivery to a memory, said memory having locations therein for the storage of said data, said locations being divided into addressable byte locations, CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said input channels with said periodic control intervals, means resonsive to requests for data for delivery to said memory from a particular input channel for addressing certain of said bytes of data in said memory during said control interval uniquely associated with said particular input channel, means operative during each said control interval for removing m+1 bytes of data from said input channels, said m+1 bytes consisting of a data byte for delivery to an addressed byte location within said memory plus m data bytes for delivery to m sequenced byte locations within said memory which are contiguous to said addressed location from said channel plus data bytes from m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said input channels and with said control interval associated with said particular input channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said input channels to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data stored in each said buffer memory segment to said associated buffer memory segments.
Claim 22
Dependent Claim
273 words
A circuit for removing data from an input channel for concurrent delivery to a memory, said memory having locations therein for the storage of said data, said locations being divided into addressable byte locations, CHARACTERISED IN THAT said circuit comprises means for generating periodic control intervals, means for associating on a one-to-one basis certain of said input channels with said periodic control intervals, means resonsive to requests for data for delivery to said memory from a particular input channel for addressing certain of said bytes of data in said memory during said control interval uniquely associated with said particular input channel, means operative during each said control interval for removing m+1 bytes of data from said input channels, said m+1 bytes consisting of a data byte for delivery to an addressed byte location within said memory plus m data bytes for delivery to m sequenced byte locations within said memory which are contiguous to said addressed location from said channel plus data bytes from m sequenced data storage areas which are contiguous to said addressed data storage area, a buffer memory divided into segments, each segment associable with a particular one of said input channels and with said control interval associated with said particular input channels, each such segment having storage capability for m+1 bytes of data, means operative during each said control interval for transferring said removed m+1 bytes of data from said input channels to said buffer memory and for storing said transferred data in said segment associated with said control interval, and means for sequentially transferring data stored in each said buffer memory segment to said associated buffer memory segments.
Claim 23
Dependent Claim
69 words
The circuit set forth in claim 17, CHARACTERISED IN THAT said buffer memory is arranged with a pair of segments associated with each said control interval and wherein data which is transferred to said buffer memory is stored alternately in said paired segments, and means for transferring data from a first one of said paired segments while data is being transferred into the other one of said paired segments.
References Cited (Backward Citations)
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