Patent EP0258808A2 successfully refreshed from Google Patents.
EP0258808A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Complementary mos integrated circuit
Assignee: Mitsubishi Electric Corp
•
Filing: 1987-08-26
•
Granted: —
•
Expires: 2007-08-26
Abstract
Abstract A complemenary MOS integrated circuit comprising an output circuit and a pre-output circuit, which is capable of reducing a penetration current which occurs upon switching of transistors in the output circuit, to thereby suppress an occurrence of spike noises in an output signal. The pre-output circuit comprises MOS transistors constituting an analog switch, "on-resistances" of which are utilized as a resistor, and MOS transistor gates. A series circuit of the analog switch and the gates are coupled in series with a power source.
Inventors
- 👤 Takenori C/O Mitsubishi Denki Okitaka
- 👤 Yukio C/O Mitsubishi Denki Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/0008; H03K19/0013; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
113 words
(1) A complementary MOS integrated circuit characterized by:a data input terminal; an output circuit including a first P-channel MOS transistor and a first N-channel transistor connected in series with each other, said output circuit being coupled between first and second power source terminals and an output signal being produced from a common coupling point of said first P-channel and N-channel MOS transistors; and a pre-output circuit adapted to drive said output circuit, which is coupled between said first and second power source terminals in parallel with said output circuit, said pre-output circuit including a first gate means, a second gate means and a resistance means connected between said first and second gate means.
Claim 2
Dependent Claim
111 words
(2) The circuit as defined in claim 1 characterized in that said first gate means is a second P-channel MOS transistor having a gate terminal connected to said data input terminal, said second gate means is a second N-channel MOS transistor having a gate terminal connected to said data input terminal and said resistance means includes third P-channel and N-channel MOS transistors coupled in parallel with each other to constitute a first analog switch, and wherein said resistance means is connected between drain electrodes of said second P-channel and N-channel MOS transistors, and gate electrodes of said third P-channel and N-channel MOS transistors are commonly connected to said data input terminal.
Claim 3
Dependent Claim
294 words
(3) The circuit as defined in claim 1 characterized in that a second analog switch including a fifth P-channel MOS transistor whose gate is connected to a first control input terminal and a fifth N-channel MOS transistor whose gate is connected to a second control input terminal, said fifth P-channel and N-channel MOS transistors being connected in parallel with each other, said first gate means including a second P-channel MOS transistor whose gate is connected to said data input terminal and a fourth P-channel MOS transistor whose gate is connected to said second control input terminal, said second and fourth P-channel MOS transistor being connected in parallel with each other between said first power source terminal and the gate of said first P-channel MOS transistor of said output circuit; said second gate means including a second N-channel MOS transistor whose gate is connected to said data input terminal and a fourth N-channel MOS transistor whose gate is connected to said first control input terminal to receive a first control signal which is opposite in logic level to a second control signal applied to said second control input terminal, said second and fourth N-channel MOS transistors being connected in parallel with each other between the gate of said first N-channel MOS transistor and said second power source terminal; and said resistance means including a third P-channel MOS transistor whose gate is connected to said data input terminal and a third N-channel MOS transistor whose gate is connected to said data input terminal, said third P-channel and N-channel MOS transistors being connected in parallel with each other to constitute a first analog switch, said first and second analog switches being series-connected between the gates of said first P-channel and N-channel MOS transistors of said output circuit.
Claim 4
Dependent Claim
42 words
(4) The circuit as defined in claim 3 characterized in that a series circuit of said first gate means, said first analog switch, said second analog switch and said second gate means is connected between said first and second power source terminals.
Claim 5
Dependent Claim
42 words
(5) The circuit as defined in claim 3 characterized in that a series circuit of said first gate means, said second analog switch, said first analog switch and said second gate means is connected between said first and second power source terminals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.