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EP0257948A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Conductive via plug for CMOS devices

Assignee: AT&T Inc
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Filing: 1987-08-17
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Granted: —
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Expires: 2007-08-17
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Abstract

Abstract A material such as boron nitride is conformally deposited and then patterned to form adherent portions (22) on the sidewalls of high-aspect-ratio vias (18) formed in a dielectric layer (16) of a CMOS device. A conductive material such as tungsten is then selectively deposited in the vias on the boron nitride and on silicon or silicide at the via bottoms. In some cases, the deposition of tungsten is controlled to fill the vias thereby leaving an advantageous substantially planar surface for subsequent metallization.

Inventors

  • 👤 Roland Albert Levy

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 15:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10W20/071; H10W20/074; H10W20/076; H10W20/40; H10W20/41; H10W20/42

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 105 words
A semiconductor device comprising a dielectric layer (16) having at least one via (18) formed therethrough, each via (18) including a sidewall defined by a portion of said layer (16), and means (10,14) supporting said dielectrical layer (16), CHARACTERISED IN THAT an adherent liner layer (22) is in contact with the sidewall of each via (18) and with a limited portionof the supporting means at the bottom of each via (18), and an electrically conductive material (24) within said via (18) is adherently attached to said liner layer (22) and to the remaining portion of the supporting means at the bottom of each via (18).
Claim 2
Dependent Claim 105 words
A semiconductor device comprising a dielectric layer (16) having at least one via (18) formed therethrough, each via (18) including a sidewall defined by a portion of said layer (16), and means (10,14) supporting said dielectrical layer (16), CHARACTERISED IN THAT an adherent liner layer (22) is in contact with the sidewall of each via (18) and with a limited portionof the supporting means at the bottom of each via (18), and an electrically conductive material (24) within said via (18) is adherently attached to said liner layer (22) and to the remaining portion of the supporting means at the bottom of each via (18).
Claim 3
Dependent Claim 29 words
A device as in claim 1 CHARACTERISED IN THAT said device comprises a CMOS device and said at least one via (18) is characterised by a high aspect ratio.
Claim 4
Dependent Claim 18 words
A device as in claim 2, CHARACTERISED IN THAT said liner layer (22) comprises conformally deposited boron nitride.
Claim 5
Dependent Claim 17 words
A device as in claim 3, CHARACTERISED IN THAT said conductive material (24) comprises conformally deposited tungsten.
Claim 6
Dependent Claim 16 words
A device as in claim 4, CHARACTERISED IN THAT said limited portion comprises a metal silicide.
Claim 7
Dependent Claim 15 words
A device as in claim 5, CHARACTERISED IN THAT said metal silicide comprises cobalt silicide.
Claim 8
Dependent Claim 14 words
A device as in claim 4, CHARACTERISED IN THAT said limited portion comprises silicon.
Claim 9
Dependent Claim 17 words
A device as in claim 6, CHARACTERISED IN THAT said dielectric layer (16) comprises a glass material.
Claim 10
Dependent Claim 31 words
A device as in claim 8, CHARACTERISED IN THAT the top surface of said liner layer (22) within each via (18) is below the top surface of said dielectric layer (16).
Claim 11
Dependent Claim 29 words
A device as in claim 9, CHARACTERISED IN THAT the top surface of said conductive material (24) is substantially coplanar with the top surface of said dielectric layer (16).
Claim 12
Dependent Claim 19 words
A device as in claim 10 further CHARACTERISED BY a patterned conductive layer (26) deposited on said top surfaces.
Claim 13
Dependent Claim 16 words
A device as in claim 11, CHARACTERISED IN THAT said patterned conductive layer (26) comprises aluminum.
Claim 14
Dependent Claim 20 words
A device as in claim 12, further CHARACTERISED BY a metal silicide layer (28) on said patterned conductive layer (26).
Claim 15
Dependent Claim 124 words
A device as in claim 13 still further CHARACTERISED BY a dielectric layer (30) on said patterned conductive layer (26), said dielectric layer (30) having at least one via formed therethrough, each via including a sidewall defined by a portion of said second-mentioned dielectric layer (30), an adherent liner layer (32) in contact with the sidewall of each via in said second-mentioned dielectric layer (30) and in contact with a limited portion of the silicide layer (28) at the bottom of each such via, and an electrically conductive material (34) within each via in said second-mentioned dielectric layer (30) and adhered to the liner layer (32) therein and to the remaining portion of the silicide layer (28) at the bottom of each such via.
Claim 16
Independent Claim 161 words
A method of fabricating a semiconductor device of the type that includes a dielectric layer (16) having at least one via (18) formed therethrough, the supporting surface for said dielectric layer (16) comprising a surface of a metal, metal silicide or silicon at the bottom of each via (18), said method comprising the step of conformally depositing a uniform adherent layer (20) on the top surface of said dielectric layer (16) and on the sidewall and bottom of each via (18), said method being CHARACTERISED BY the steps of anisotropically etching said adherent layer (20) to leave portions thereof only on the sidewall of each via (18), conformally depositing a conductive material (24) only on said sidewall portion and on the surface at the bottom of each via to form a conductive plug therein, and forming a conductive pattern (26) on the top surface of said dielectric layer (16) and in contact with at least one of said conductive via plugs.
Claim 17
Independent Claim 161 words
A method of fabricating a semiconductor device of the type that includes a dielectric layer (16) having at least one via (18) formed therethrough, the supporting surface for said dielectric layer (16) comprising a surface of a metal, metal silicide or silicon at the bottom of each via (18), said method comprising the step of conformally depositing a uniform adherent layer (20) on the top surface of said dielectric layer (16) and on the sidewall and bottom of each via (18), said method being CHARACTERISED BY the steps of anisotropically etching said adherent layer (20) to leave portions thereof only on the sidewall of each via (18), conformally depositing a conductive material (24) only on said sidewall portion and on the surface at the bottom of each via to form a conductive plug therein, and forming a conductive pattern (26) on the top surface of said dielectric layer (16) and in contact with at least one of said conductive via plugs.
Claim 18
Dependent Claim 22 words
A method as in claim 15, CHARACTERISED IN THAT said uniform adherent layer (20) comprises boron nitride deposited in a CVD step.
Claim 19
Dependent Claim 28 words
A method as in claim 16, CHARACTERISED IN THAT said etching step comprises reactive ion etching said boron nitride layer in a plasma derived from CF₄ and 0₂.
Claim 20
Dependent Claim 19 words
A method as in claim 17, CHARACTERISED IN THAT said conductive material comprises tungsten deposited in a CVD step.
Claim 21
Dependent Claim 15 words
A method as in claim 18, CHARACTERISED IN THAT said conductive pattern (26) comprises aluminum.
Claim 22
Dependent Claim 33 words
A method as in claim 15, CHARACTERISED IN THAT said conductive material is formed by depositing a metal and either partially or completely reacting said metal with underlying material to form a silicide.
Claim 23
Dependent Claim 16 words
A method as in claim 20. CHARACTERISED IN THAT said silicide is formed during metal deposition.
Claim 24
Dependent Claim 18 words
A method as in claim 20 CHARACTERISED IN THAT said silicide is formed in a post-deposition annealing step.

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