Digital memory with reset/preset capabilities

Claim 2

A digital memory comprising: a plurality of memory cells arranged in a matrix having rows and columns, and means coupled to said matrix for substantially concurrently varying the contents of said memory cells.

Claim 3

A digital memory as recited in claim 1 wherein said means coupled to said matrix can preset said memory cells.

Claim 4

A digital memory as recited in claim 1 wherein said means coupled to said matrix can reset said memory cells.

Claim 5

A digital memory as recited in claim 3 wherein said means coupled to said matrix can preset said memory cells.

Claim 6

A digital memory as recited in claim 4 wherein said means coupled to said matrix includes row activation means coupled to said rows, and column reset/preset means coupled to said columns.

Claim 7

A digital memory as recited in claim 5 wherein said column reset/preset means includes a plurality of switch means coupled to said columns, and reset/preset logic means for selectively opening and closing said switch means.

Claim 8

A digital memory as recited in claim 6 wherein said column reset/preset means further includes a column reset line and a column preset line for each of said columns, where each column reset line and each column preset line is coupled to one of said plurality of switch means.

Claim 9

A digital memory as recited in claim 7 where said plurality of switch means couple said column reset lines and said column preset lines to a constant current source.

Claim 10

A digital memory as recited in claim 5 wherein said row activation means includes a row decoder coupled to said rows and a row address buffer coupled to said row decoder, said row address buffer being responsive to a reset/preset signal and operative to either cause said row decoder to activate all of said rows or one of said rows in response thereto.

Claim 13

A method as recited in claim 10 wherein the same column signal is applied to all of said columns.

Claim 14

A method as recited in claim 11 wherein said column signal is either a reset signal which resets the memory cells of the matrix, or a preset signal which presets the memory cells of the matrix.

Claim 15

A method as recited in claim 10 wherein different column signals are applied to said columns.

Claim 16

A method as recited in claim 13 wherein said different column signals are either a reset signal which can reset the memory cells of the column to which it is applied, or a preset signal which can preset the memory cells of the column to which it is applied.

Claim 17

A digital memory comprising: a plurality of memory cells arranged in a matrix having rows and columns, wherein each row has an associated row activation line, wherein each column has an associated reset line and an associated preset line, wherein each memory cell is coupled to the row activation means of the row of which it forms a part, and wherein each memory cell is coupled to the reset line and the preset line of the column of which it forms a part; row activation means for concurrently activating all of said row activation lines; and column activation means for concurrently activating either the reset line or the preset line of each of said columns.

Claim 18

A digital memory comprising: a plurality of memory cells arranged in a matrix having rows and columns, wherein each row has an associated row activation line, wherein each column has an associated reset line and an associated preset line, wherein each memory cell is coupled to the row activation means of the row of which it forms a part, and wherein each memory cell is coupled to the reset line and the preset line of the column of which it forms a part; row activation means for concurrently activating all of said row activation lines; and column activation means for concurrently activating either the reset line or the preset line of each of said columns.

Claim 19

A digital memory as recited in claim 15 wherein each of said row activation lines is an upper word line and further comprising a lower word line associated with each of said rows, wherein each memory cell is coupled to the upper word line and the lower word line of the row of which is forms a part; and wherein each column of said matrix is further provided with a first bit line and a second bit line, wherein each memory cell is coupled to the first bit line and the second bit line of the column of which it forms a part.

Claim 20

A digital memory as recited in claim 16 wherein each memory cell includes an upper node coupled to said upper word line, a lower node coupled to said lower word line, a reset node coupled to said reset line, and a preset node coupled to said preset line.

Claim 21

A digital memory as recited in claim 17 wherein said reset node is coupled to said reset line by first rectification means, and wherein said preset node is coupled to said preset line by second rectification means.

Claim 22

A digital memory as recited in claim 15 wherein said row activation means includes a row address buffer responsive to a row address and to a reset/preset signal, and a row decoder having inputs coupled to said row address buffer and outputs coupled to said row activation lines, whereby said row decoder is operative to either activate a single row or all of said rows in response to said reset/preset signal.

Claim 23

A digital memory as recited in claim 15 wherein said column activation means includes a plurality of switch means coupled to each of said reset lines and said preset lines for their selective activation, and reset/preset control logic coupled and controlling said switch means.

Claim 24

A digital memory as recited in claim 20 wherein said switch means are coupled to a current source.

Claim 25

A digital memory cell for use in a digital matrix having rows and columns, where each row is provided with an upper word line and a lower word line, and each column is provided with a first bit line, a second bit line, a reset line, and a preset line, said digital memory cell comprising: first transistor means having a first emitter, a first base, and a first collector, where said first emitter is coupled to said upper word line; second transistor means having a second emitter, a second base, and a second collector, said second emitter being coupled to said upper word line and said second collector being coupled to said first base; third transistor means having a third bit emitter, a third standby emitter, a third base, and a third collector, where said third bit emitter is coupled to said first bit line, said third standby emitter is coupled to said lower word line, said third base is coupled to said first collector and said second base, and said third collector is coupled to said first base; fourth transistor means having a fourth bit emitter, a fourth standby emitter, a fourth base, and a fourth collector, where said fourth bit emitter is coupled to said second bit line, said fourth standby emitter is coupled to said lower word line, said fourth base is coupled to said first base and said second collector, and said fourth collector is coupled to said second base; first means coupling said first base to said reset line; and second means coupling said second base to said preset line.

Claim 26

A digital memory cell for use in a digital matrix having rows and columns, where each row is provided with an upper word line and a lower word line, and each column is provided with a first bit line, a second bit line, a reset line, and a preset line, said digital memory cell comprising: first transistor means having a first emitter, a first base, and a first collector, where said first emitter is coupled to said upper word line; second transistor means having a second emitter, a second base, and a second collector, said second emitter being coupled to said upper word line and said second collector being coupled to said first base; third transistor means having a third bit emitter, a third standby emitter, a third base, and a third collector, where said third bit emitter is coupled to said first bit line, said third standby emitter is coupled to said lower word line, said third base is coupled to said first collector and said second base, and said third collector is coupled to said first base; fourth transistor means having a fourth bit emitter, a fourth standby emitter, a fourth base, and a fourth collector, where said fourth bit emitter is coupled to said second bit line, said fourth standby emitter is coupled to said lower word line, said fourth base is coupled to said first base and said second collector, and said fourth collector is coupled to said second base; first means coupling said first base to said reset line; and second means coupling said second base to said preset line.

Claim 27

A memory cell as recited in claim 22 wherein said first means includes a first diode having a first anode coupled to said first base and a first cathode coupled to said reset line, and wherein said second means includes a second diode having a second anode coupled to said second base and a second cathode coupled to said preset line.

Claim 28

An integrated circuit device including a plurality of reset/preset memory cells, wherein each reset/preset memory cell includes: a substrate having a first conductivity type; a high conductivity layer formed over said substrate and having a second conductivity type; an intermediate layer formed over said high conductivity layer and having said second conductivity type; diode means formed into said intermediate layer; first transistor means of a first configuration formed into said intermediate layer; and second transistor means of a second configuration formed into said intermediate layer.

Claim 29

An integrated circuit device including a plurality of reset/preset memory cells, wherein each reset/preset memory cell includes: a substrate having a first conductivity type; a high conductivity layer formed over said substrate and having a second conductivity type; an intermediate layer formed over said high conductivity layer and having said second conductivity type; diode means formed into said intermediate layer; first transistor means of a first configuration formed into said intermediate layer; and second transistor means of a second configuration formed into said intermediate layer.

Claim 30

An integrated circuit device as recited in claim 24 wherein a portion of said diode means and a portion of said first transistor means are in intimate contact with said high conductivity layer.

Claim 31

An integrated circuit device as recited in claim 25 wherein said high conductivity layer includes a riser portion which is in intimate contact with said portion of said diode means and said portion of said first transistor means.

Claim 32

An integrated circuit device as recited in claim 26 wherein said riser portion bifurcates said intermediate layer so that said diode means is located on a first side of said riser portion, and said first transistor means is located on a second side of said riser portion.

Claim 33

An integrated circuit device as recited in claim 27 wherein a portion of said second transistor means is in intimate contact with a portion of said first transistor means.

Claim 34

An integrated circuit device as recited in claim 24 wherein a portion of second transistor means is in intimate contact with a portion of said first transistor means.

Claim 35

An integrated circuit device as recited in claim 24 wherein said diode means includes a diode well of said first conductivity type formed into said intermediate layer, a first diode region of said second conductivity type formed into said diode well, and a second diode region of said first conductivity type formed in said diode well, where said second diode region is in intimate contact with said high conductivity layer.

Claim 36

An integrated circuit device as recited in claim 24 wherein said first transistor means includes a first region of said first conductivity type formed into said intermediate layer and a second region of said first conductivity type formed into said intermediate layer, where said first region of said first transistor means is in intimate contact with said high conductivity layer.

Claim 37

An integrated circuit device as recited in claim 30 wherein said first transistor means includes a first region of said first conductivity type formed into said intermediate layer, and a second region of said first conductivity type formed into said intermediate layer, where said first region of said first transistor means is in intimate contact with said high conductivity layer.

Claim 38

An integrated circuit device as recited in claim 24 wherein said second transistor means includes a transistor well of said first conductivity type formed into said intermediate layer, a first region of said second conductivity type formed into said transistor well, and a second region of said second conductivity device formed into said transistor well.

Claim 39

An integrated circuit device as recited in claim 32 wherein said second transistor means includes a transistor well of said first conductivity type formed into said intermediate layer, a third region of said second conductivity type formed into said transistor well, and a fourth region of said second conductivity device formed into said transistor well, where said transistor well is in intimate contact with said second region of said first transistor means.

Claim 40

An integrated circuit device as recited in claim 24 wherein said diode means is a first diode means, and further comprising second diode means formed into said intermediate layer as a mirror image of said first diode means, third transistor means formed into said intermediate layer as a mirror image of said first transistor means, and fourth transistor means formed into said intermediate layer as a mirror image of said second transistor means.

Claim 41

An integrated circuit device as recited in claim 34 wherein said diode means is a first diode means, and further comprising second diode means formed into said intermediate layer as a mirror image of said first diode means, third transistor means formed into said intermediate layer as a mirror image of said first transistor means, and fourth transistor means formed into said intermediate layer as a mirror image of said second transistor means.