Patent EP0257437A2 successfully refreshed from Google Patents.
EP0257437A2
Expired / Lapsed
EP
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Master slice type integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1987-08-11
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Granted: —
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Expires: 2007-08-11
Abstract
Abstract A semiconductor circuit comprises basic cells formed in an internal cell region on an integrated-circuit chip and pads (22₁, 22₂, ..., 22 n ) for input/output cells, the pads being arranged in peripheral regions on said chip. The semiconductor circuit further comprises first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of the input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, the first logic circuit means being positioned in the peripheral regions. The present invention also comprises second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of the input/output cells, each including remaining logic circuits of the respective input/output cells, the second logic circuit being formed by the basic cells formed in the internal cell regions, so that each of said input/output cells is formed by one pad and the combination of the first and second logic circuit means.
Inventors
- 👤 Yoshiyuki Suehiro
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 17:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/026; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W72/90; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A semiconductor device comprising basic cells formed in an internal cell region on an integrated-circuit chip (2l); pads (22₁, 22₂, ..., 22 n ) for input/output cells, said pads being arranged in peripheral regions on said chip; first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of said input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, said first logic circuit means being positioned in said peripheral regions; and second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of said input/output cells, each including remaining logic circuits of said respective input/output cells, said second logic circuit being formed by said basic cells formed in said internal cell region, so that each of said input/output cells is formed by one pad and the combination of said first and second logic circuit means.
Claim 2
Dependent Claim
153 words
A semiconductor device comprising basic cells formed in an internal cell region on an integrated-circuit chip (2l); pads (22₁, 22₂, ..., 22 n ) for input/output cells, said pads being arranged in peripheral regions on said chip; first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of said input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, said first logic circuit means being positioned in said peripheral regions; and second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of said input/output cells, each including remaining logic circuits of said respective input/output cells, said second logic circuit being formed by said basic cells formed in said internal cell region, so that each of said input/output cells is formed by one pad and the combination of said first and second logic circuit means.
Claim 3
Dependent Claim
47 words
A semiconductor device as claimed in claim l, characterized in that the mutual conductance of transistors forming said logic circuits included in said first logic circuit means is approximately ten to twenty times larger than of transistors forming said logic circuits included in said second logic circuit.
Claim 4
Dependent Claim
39 words
A semiconductor device as claimed in claim l or 2. characterized in that said first logic circuit each comprises a protection circuit (62, 72, 83) for protecting said first and second logic circuits against over-voltage resulting from electrostatic discharge.
Claim 5
Dependent Claim
34 words
A semiconductor device as claimed in any one of claims l to 3, characterized in that said transistors included in said first logic circuit is formed by the combination of transistors connected in parallel.
Claim 6
Dependent Claim
31 words
A semiconductor device as claimed in any one of claims l to 4, characterized in that said first logic circuit means and said relative pad for each input/output cell are aligned.
Claim 7
Dependent Claim
52 words
A semiconductor device as claimed in any one of claims l to 5, characterized in that a part (22₁, 22₂) of said pads located in the vicinity of corners of said chip are located at positions closer to said chip corners than positions of said corresponding first logic circuit means (23₁, 23₂).
Claim 8
Dependent Claim
200 words
A semiconductor device comprising basic cells formed in an internal cell region on an integrated-circuit chip (2l); pads (22₁, 22₂, ..., 22 n ) for input buffer cells of cascade-connected transistors (64a, 64b, 64c, 63), said pads being arranged in peripheral regions on said chip; first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of said input buffer cells, each including a transistor circuit (63) at a final stage of said respective input buffer cells as well as a protection circuit (62) connected to said corresponding pad for protecting said respective input buffer cells, said first logic circuit means being positioned in said peripheral regions; and second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of said input buffer cells, each including remaining transistor circuits (64a, 64b, 64c) of said respective input buffer cells, said second logic circuit being formed by said basic cells formed in said internal cell regions, an output of said second logic circuit means being connected to an input of said first logic circuit means, so that each of said input/output cells is formed by one pad and the combination of said first and second logic circuit means.
Claim 9
Dependent Claim
200 words
A semiconductor device comprising basic cells formed in an internal cell region on an integrated-circuit chip (2l); pads (22₁, 22₂, ..., 22 n ) for input buffer cells of cascade-connected transistors (64a, 64b, 64c, 63), said pads being arranged in peripheral regions on said chip; first logic circuit means (23₁, 23₂, ..., 23 n ) provided for each of said input buffer cells, each including a transistor circuit (63) at a final stage of said respective input buffer cells as well as a protection circuit (62) connected to said corresponding pad for protecting said respective input buffer cells, said first logic circuit means being positioned in said peripheral regions; and second logic circuit means (25₁, 25₂, ..., 25 n ) provided for each of said input buffer cells, each including remaining transistor circuits (64a, 64b, 64c) of said respective input buffer cells, said second logic circuit being formed by said basic cells formed in said internal cell regions, an output of said second logic circuit means being connected to an input of said first logic circuit means, so that each of said input/output cells is formed by one pad and the combination of said first and second logic circuit means.
Claim 10
Dependent Claim
32 words
A semiconductor circuit as claimed in claim 7, characterized in that said transistors forming said final stage in each of said first logic circuit means are formed by transistors connected in parallel.
References Cited (Backward Citations)
No citation records indexed.
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