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EP0256918A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Temperature compensated BFL logic gate

Assignee: Thales SA
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Filing: 1987-07-28
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Granted: —
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Expires: 2007-07-28
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Abstract

Abstract The invention relates to a logic gate of BFL type, that is to say "Buffered FET Logic", constructed with "normally conducting" transistors made with group III-V materials such as GaAs, and which is intended for fast logic operations. A BFL logic gate comprises an input stage (1, 2) and an output stage in which an intermediate transistor (3) fed by a current source (4) draws a current (ID) across an offsetting diode (5). If the temperature varies the voltage drop (VD) in the offsetting diode (5) varies, and the output signal (V0) may no longer clamp the input transistor (1') of a succeeding BFL gate. For temperature compensation, a compensating diode (9) is mounted within the bias (VGS) of the current-source transistor (4). The current (ID) drawn varies inversely with the drop in the voltage (Vc) in the compensating diode (9) and re-establishes the voltage drop (VD) in the offsetting diode (5). Application to fast logic circuits. <IMAGE>

Inventors

  • 👤 Ernesto Perea

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 22:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K19/003; H03K19/00369; H03K19/00384

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

DE3336949A1 Cited

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