Nonvolatile semiconductor memory including means for detecting completion of writing operation

Claim 2

A semiconductor memory comprising a plurality of memory transistors, means responsive to a set of address signals for selecting at least one of said memory transistors, means for applying a programming voltage to the selected memory transistor, a threshold voltage of each of said memory transistors being changed when said programming voltage is applied thereto, means coupled to said selected memory transistor for detecting the change in the threshold voltage thereof to produce a detection signal, and means responsive to said detection signal for stopping the application of said programming voltage to the selected memory transistor.

Claim 3

The memory as claimed in claim 1, wherein each of said memory transistors has a control gate, a floating gate, a drain and a source.

Claim 4

The memory as claimed in claim 1, further comprising an output terminal through which said detection signal is outputted externally.

Claim 5

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, means response to a set of address signals for selecting at least one memory transistor, means for applying a programming voltage between said control gate and said drain of said at least one memory transistor to charge said floating gate thereof at a predetermined value, means coupled to said source of said at least one memory transistor for detecting a potential change at said source caused by a change in a threshold voltage of said at least one memory transistor and thereby producing a detection signal, and means responsive to said detection signal for preventing said programming voltage from being applied to said at least one memory transistor.

Claim 6

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, means response to a set of address signals for selecting at least one memory transistor, means for applying a programming voltage between said control gate and said drain of said at least one memory transistor to charge said floating gate thereof at a predetermined value, means coupled to said source of said at least one memory transistor for detecting a potential change at said source caused by a change in a threshold voltage of said at least one memory transistor and thereby producing a detection signal, and means responsive to said detection signal for preventing said programming voltage from being applied to said at least one memory transistor.

Claim 7

The memory as claimed in claim 4, further comprising means activated in a data-reading mode for reading data of said at least one memory transistor and means activated in said data-reading mode for connecting said source of said at least one memory transistor to a reference terminal to clamp said source to a reference potential at said reference terminal.

Claim 8

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, an address decoder responding to a set of address signals for selecting at least one of said memory transistors, a data writing circuit activated in a data writing mode and supplying a writing voltage between said control gate and said drain of the selected memory transistor, a reference terminal, a source potential control circuit disconnecting said source of said selected memory transistor from said reference terminal in said data writing mode, a source potential detection circuit comparing a potential at said source of said selected memory transistor with a reference voltage and producing an output signal when said potential exceeds said reference voltage, and means responsive to said output signal for inactivating said data write circuit.

Claim 9

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, an address decoder responding to a set of address signals for selecting at least one of said memory transistors, a data writing circuit activated in a data writing mode and supplying a writing voltage between said control gate and said drain of the selected memory transistor, a reference terminal, a source potential control circuit disconnecting said source of said selected memory transistor from said reference terminal in said data writing mode, a source potential detection circuit comparing a potential at said source of said selected memory transistor with a reference voltage and producing an output signal when said potential exceeds said reference voltage, and means responsive to said output signal for inactivating said data write circuit.

Claim 10

The memory as claimed in claim 6, wherein said source potential detection circuit connects said source of said selected memory transistor to said reference terminal in a data reading mode.

Claim 11

The memory as claimed in claim 7, wherein said source potential detection circuit includes a first transistor connected between a voltage terminal and said source and turned ON in said data writing mode and OFF in said data reading mode and a second transistor connected between said reference terminal and said source and turned OFF in said data writing mode and ON in said data reading mode.

Claim 12

The memory as claimed in claim 8, wherein said first transistor is changed to the OFF state irrespective of said data writing mode when said potential at said source is raised.