Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors

Claim 1

Process for making structures including E²PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors consisting of the steps (a) deposit of a first layer of polycrystalline silicon (4) on a substrate of monocrystalline silicon (1) furnished in advance with field oxide (2) and gate oxide (3), (b) definition and etching of said first silicon layer (4), (c) growth of a thin layer of oxide (5) on said first silicon layer (4), (d) etching of said oxide layer (5) in the area intended for formation of the transistors, (e) deposit of a second layer of polycrystalline silicon (11) and (f) final etching of the two silicon layers (4, 11) and of the intermediate oxide layer (5) at the sides of the cell and transistor areas characterized in that at least in the area intended for formation of the selection transistor (16) etching of the intermediate oxide layer (5) is limited to the formation of a window (9, 10) narrower than that desired for said transistor and in that final etching of the two silicon layers (4, 11) and of the intermediate oxide layer (5) is performed using a mask (13, 26) formed in such a manner as to superimpose on the second silicon layer (11), at least in the selection transistor area (16), a covering wider than the corresponding window (9, 20) of the intermediate oxide layer (5).