Patent EP0255090A2 successfully refreshed from Google Patents.
EP0255090A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
LAN controller proprietary bus
Assignee: Bull HN Information Systems Inc
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Filing: 1987-07-27
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Granted: —
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Expires: 2007-07-27
Abstract
Abstract A local area network (LAN) controller proprietary bus is disclosed comprised of a multiprocessor (µP) bus, a direct memory access bus, and an adapter bus. The bus permits the attachment of various computer elements while providing other integrity and communication functions to other computer elements or computer systems beyond the bus. The proprietary bus includes an adapter interface having up to four daughterboards. Each daughterboard has odd and even numbered connectors. Certain daughterboards are designed to handle control lines; whereas other daughterboards handle data and address lines. These daughterboards are the hardware means by which communications with LANs which are attached to the proprietary bus are accomplished with processes, disks, tapes, memories, attached to the proprietary bus.
Inventors
- 👤 Edward Beauchemin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 07:02
CPC Classifications
H; H04; H04L; H04L5/00; G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/128; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; H04L12/00; H04L12/28; H04L12/46; H04L69/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
116 words
A controller having a computer interface between a proprietary bus and at least one local area network (LAN) system for coupling a plurality of different types of LANs to said controller, said proprietary bus comprising: (a) a microprocessor bus having coupled to it at least a first microprocessor (µP); (b) a direct memory (DMA) bus having coupled to it at least a first memory, said µP bus being coupled to said DMA bus by first transmit/receive means for transmitting/receiving information between said µP bus and said DMA bus; and, (c) an adapter bus coupled to said DMA bus, and including an adapter interface for coupling said proprietary bus to said plurality of different types of LANs.
Claim 2
Dependent Claim
116 words
A controller having a computer interface between a proprietary bus and at least one local area network (LAN) system for coupling a plurality of different types of LANs to said controller, said proprietary bus comprising: (a) a microprocessor bus having coupled to it at least a first microprocessor (µP); (b) a direct memory (DMA) bus having coupled to it at least a first memory, said µP bus being coupled to said DMA bus by first transmit/receive means for transmitting/receiving information between said µP bus and said DMA bus; and, (c) an adapter bus coupled to said DMA bus, and including an adapter interface for coupling said proprietary bus to said plurality of different types of LANs.
Claim 3
Dependent Claim
25 words
The controller as recited in Claim 1 wherein said adapter interface includes at least one connector for connecting said adapter bus to said DMA bus.
Claim 4
Dependent Claim
32 words
The controller as recited in Claim 1 wherein said adapter interface includes at least eight connectors W01-W08, and wherein all even numbered connectors W02, W04, W06, W08, handles data and address signals.
Claim 5
Dependent Claim
15 words
The controller as recited in Claim 3 wherein said connector numbered 01 handles control signals.
Claim 6
Dependent Claim
33 words
The controller as recited in Claim 4 wherein each connector has at least 54 terminals and wherein connector W01 includes terminals for transmitting/receiving signals for bus clear, read/write, master clear and error indication.
Claim 7
Dependent Claim
23 words
The controller as recited in Claim 2 wherein said adapter interface includes first transceivers for coupling said DMA bus to said adapter bus.
Claim 8
Dependent Claim
24 words
The controller as recited in Claim 7 wherein said first transmit/receive means includes second transceivers for coupling said µP bus to said DMA bus.
Claim 9
Dependent Claim
22 words
The controller as recited in Claim 8 wherein said µP bus further comprises a µP control signal bus and aµP data/address bus.
Claim 10
Dependent Claim
23 words
The controller as recited in Claim 9 including an erasable programmable read only memory (EPROM) coupled to said µP data and address bus.
Claim 11
Dependent Claim
19 words
The controller as recited in Claim 10 including a timing controller coupled to said µP data and address bus.
References Cited (Backward Citations)
No citation records indexed.
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