Semiconductor memory device

Claim 1

A semiconductor memory device comprising a memory cell, which memory cell comprises: a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode (25) connected to a word line, a drain and a source, the source being connected to a bit line (31); a charge storage electrode (28) connected to the drain of the first transistor a semiconductor layer (29,30,31) formed over the charge storage electrode, being separated from the charge storage electrode by an insulating film; a second MOS transistor (Q2) of a second channel type different from the first channel type, formed in the semiconductor layer and having a source and a drain, the charge storage electrode of the first MOS transistor forming a gate of the second MOS transistor; the drain of the second transistor being connected to a power supply; the source of the second transistor being connected to a bit line, which is either the same as or separate from the first-mentioned bit line; said memory device further comprising means for controlling writting and reading of data in and out of the memory cell; said control means writting daa by controlling the potential on the word line the bit line connected to the first MOS transistor to supply an electric charge corresponding to the data on the bit line connected to the first MOS transistor; said semiconductor memory device being characterized in that said change storage electrode (28) is formed over the gate electrode of the first transistor, being separated from the gate electrode by an insulating film to form a capacitor that a diode (D1) is formed between the source of said first MOS transistor (Q1) and the but line, and that said control means reads data by controlling the potential on the word line to cause conduction or nonconduction of the second MOS transistor depending on the electric charge stored on the charge storage electrode, thereby providing an output on the bit line connected to the second MOS transistor, the output differing depending on the conduction or nonconduction of the second MOS transistor.

Claim 9

A device according to any one of the preceding claims wherein: said control means applies a first potential to the word line to make conductive the first MOS transistor for writing data, applying a first potential to the source of the first MOS transistor, for writing data "1", and applying a second potential to the source of the first MOS transistor for writing data "0"; said control means applies a second potential to the word line to keep the first transistor nonconductive for maintaining the data stored on the charge storage electrode; and said control means applies a third potential to the word line for reading data, to change the potential on the charge storage electrode to make the second MOS transistor conductive or nonconductive depending on the data stored on the charge storage electrode, thereby transmitting or not transmitting the potential from the power supply to the source of the second MOS transistor and hence to the bit line connected thereto, the transmission and non-transmission of the potential from the power supply providing different potentials on the bit line connected to the source of the second transistor.

Claim 14

A device according to any one of the preceding claims comprising a matrix of said memory cells.