Composite semiconductor device

Assignee: Hitachi Ltd

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Filing: 1987-07-13

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Granted: —

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Expires: 2007-07-13

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Abstract

Abstract Disclosed is a composite semiconductor device which comprises: a second and a third semiconductor regions (21, 22) of a second conductivity type formed in a first semiconductor region (12) of a first conductivity type independently of each other and so as to be exposed on one main surface of a semiconductor substrate (II); a fourth and a fifth semiconductor regions (31, 32) of the first conductivity type formed in the second semiconductor region (21) independently of each other and so as to be exposed on the one main surface of the semiconductor substrate; a first insulated gate electrode (54) formed on the second semiconductor region (21) located between the fifth and first semiconductor regions (32, 12) and exposed on the one main surface; a second insulated gate electrode (54) formed on the first semiconductor region (12) located between the second and third semiconductor regions (21, 22) and exposed on the one main surface; an electrode (52, 55) which shorts the fourth and third semiconductor regions (31, 22); another electrode (53) which shorts the second and fifth semiconductor regions (21, 32); and a further electrode (51) provided in the first semiconductor region (12).

Inventors

👤 Mutsuhiro Mori
👤 Tomoyuki Tanaka
👤 Yasumichi Yasuda

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-29 09:24

CPC Classifications

H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406; H10D84/101; H10D84/121

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 194 words

I. A composite semiconductor device comprising: a first semiconductor region (12) of a first conductivity type, second and third semiconductor regions (21, 22) of a second conductivity type formed in said first semiconductor region (12) isolatedly from each other so as to expose at one main surface of said semiconductor device, fourth and fifth semiconductor regions (31, 32) of the first conductivity type formed in said second semiconductor region isolatedly from each other so as to expose at said one main surface, a first insulated gate electrode (54) formed on a portion of said second semiconductor region (21) interposed between said fifth and first semiconductor regions (32, 12) and exposed at said one main surface, a second insulated gate electrode (54) formed on a portion of said first semiconductor region (12) interposed between said second and third semiconductor (21, 22) regions and exposed at said one main surface, first electrode means (52, 55) providing a short circuit between said fourth and third semiconductor regions (31, 22) second electrode means (53) providing a short circuit between said second and fifth semiconductor regions (21, 32) and third electrode means (51) connected to said first semiconductor region.

Claim 2

Dependent Claim 21 words

A composite semiconductor device according to Claim I, in which said first and second insulated gate electrodes (54) are mutually shorted.

Claim 3

Dependent Claim 34 words

A composite semiconductor device according to Claim 2, in which said first and second insulated gate electrodes (54) are integrally formed so as to spread over said first and second semiconductor regions (12, 21).

Claim 4

Dependent Claim 23 words

A composite semiconductor device according to Claim 3, in which said first, second and fourth semiconductor regions (12, 21, 31) constitute a transistor.

Claim 5

Dependent Claim 21 words

A composite semiconductor device according to Claim 4, in which said first and third semiconductor regions (12, 22) constitute a diode.

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