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EP0253264A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Binary coding circuit for OCR

Assignee: Sumitomo Electric Industries Ltd
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Filing: 1987-07-06
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Granted: —
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Expires: 2007-07-06
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Abstract

Abstract This invention provides a binary coding circuit particularly suited for use in an optical character reader which "reads" characters or symbols using a photoelectric conversion cell. A delay circuit has one input for receiving an output of the photoelectric conversion cell, and at least three separate and distinct delayed outputs providing respective delays that are different from each other. A threshold determining circuit is arranged so that when one of the delayed outputs is selected to be a binary-coding target signal, the threshold determining circuit receives as its inputs a plurality of ones of the delayed outputs including one delayed output having larger delay time than that of the binary-coding target signal and one delayed output having smaller delay time than that of the binary-coding target signal, so as to produce a threshold signal. A comparator circuit receives at a first input thereof the binary-coding target signal and receives at a second input thereof the threshold signal. It compares the binary-coding target signal with the threshold signal to thereby produce a binary signal.

Inventors

  • 👤 Naoki C/O Osaka Works Maeda

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 13:16
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10851; G06V; G06V30/00; G06V30/10; G06V30/16; G06V30/162

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 162 words
A binary coding circuit for an optical character reader which identifies characters or symbols using a photoelectric conversion cell comprising: a delay circuit having one input for receiving an output of said photoelectric conversion cell, and at least three separate and distinct delayed outputs providing respective delays that are different from each other; a threshold determining circuit arranged so that when one of said delayed outputs is selected to be a binary-coding target signal, said threshold determining circuit receives as its inputs a plurality of said delayed outputs including one delayed output having larger delay time than that of said binary-coding target signal and one delayed output having smaller delay time than that of said binary-coding target signal, so as to produce a threshold signal; and a comparator circuit having a first input receiving said binary-coding target signal and a second input receiving said threshold signal, for comparing said binary-coding target signal with said threshold signal to thereby produce a binary signal.
Claim 2
Dependent Claim 162 words
A binary coding circuit for an optical character reader which identifies characters or symbols using a photoelectric conversion cell comprising: a delay circuit having one input for receiving an output of said photoelectric conversion cell, and at least three separate and distinct delayed outputs providing respective delays that are different from each other; a threshold determining circuit arranged so that when one of said delayed outputs is selected to be a binary-coding target signal, said threshold determining circuit receives as its inputs a plurality of said delayed outputs including one delayed output having larger delay time than that of said binary-coding target signal and one delayed output having smaller delay time than that of said binary-coding target signal, so as to produce a threshold signal; and a comparator circuit having a first input receiving said binary-coding target signal and a second input receiving said threshold signal, for comparing said binary-coding target signal with said threshold signal to thereby produce a binary signal.
Claim 3
Dependent Claim 35 words
A binary coding circuit according to claim 1, wherein said threshold circuit comprises an OR circuit for use when the value of said binary-coding target signal becomes high in the area of characters or symbols.
Claim 4
Dependent Claim 34 words
A binary coding circuit according to claim 2, further comprising means for amplifying said binary-coding target signal with an amplification factor larger than said threshold signal and adding thereto a negative offset value (-A).
Claim 5
Dependent Claim 36 words
A binary coding circuit according to claim 1, wherein said threshold determining circuit comprises an AND circuit for use when the value of said binary-coding target signal becomes low in the area of characters or symbols.
Claim 6
Dependent Claim 34 words
A binary coding circuit according to claim 4, further comprising means for amplifying said binary-coding target signal with an amplification factor larger than said threshold signal and adding a positive offset value (+A} thereto.

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