Patent EP0252236A2 successfully refreshed from Google Patents.
EP0252236A2
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EP
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Vertical MOS type semiconductor device
Assignee: Toshiba Corp
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Filing: 1987-05-05
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Granted: —
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Expires: 2007-05-05
Abstract
Abstract A vertical MOS transistor which comprises p type base region (22) formed in n type substrate (21), n type source region (23) formed in the base region (22), and source electrode (28). The base region (22) involves first, second and third regions (22a, 22b, 22c). Channel region (26) is formed on the surface of first region (22a), the source region (23) is formed in second region (22b), third region (22c) contacts source electrode (28), and fourth region (22d) of base region (22) extends from third region (22c) so as to divide the source region and contact the channel region.
Inventors
- 👤 Taira Patent Division Matsunaga
- 👤 Takashi Patent Division Kimura
- 👤 Tetsuo Patent Division Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 06:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/667; H10D30/63; H10D30/791; H10D30/798; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
148 words
A vertical MOS (metal oxide semiconductor) type semiconductor device which comprises: a semiconductor substrate (21) of first conductivity type; a gate insulating layer (24) mounted on a part of said semiconductor substrate, a gate electrode (25) being provided on said gate insulating layer; a base region (22) of second conductivity type formed in a surface region of said semiconductor substrate and comprising first, second and third regions (22a, 22b, 22c), a channel region (26) being formed between the surface of said first region (22a) and said gate insulating layer, a source region (23) of said first conductivity type being formed in said second region (22b), and a source electrode (28) contacting said third region (22c); characterized in that said base region (22) further comprises a fourth region (22d) extending from said third region (22c) so as to divide said source region and also contact said channel region (26).
Claim 2
Dependent Claim
148 words
A vertical MOS (metal oxide semiconductor) type semiconductor device which comprises: a semiconductor substrate (21) of first conductivity type; a gate insulating layer (24) mounted on a part of said semiconductor substrate, a gate electrode (25) being provided on said gate insulating layer; a base region (22) of second conductivity type formed in a surface region of said semiconductor substrate and comprising first, second and third regions (22a, 22b, 22c), a channel region (26) being formed between the surface of said first region (22a) and said gate insulating layer, a source region (23) of said first conductivity type being formed in said second region (22b), and a source electrode (28) contacting said third region (22c); characterized in that said base region (22) further comprises a fourth region (22d) extending from said third region (22c) so as to divide said source region and also contact said channel region (26).
Claim 3
Dependent Claim
45 words
A semiconductor device according to claim 1, characterized in that said semiconductor device is provided with a plurality of mesh type cells (20), each having independent base region (22) and two source regions (23, 23) divided by said fourth region (22d) of said base region.
Claim 4
Dependent Claim
48 words
A semiconductor device according to claim 1, characterized in that a plurality of stripe type cells are provided, each having a common base region (22), and source regions (23) of more than two which are formed by being divided by said fourth region (22d) of said base region.
References Cited (Backward Citations)
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