Patent EP0251880A2 successfully refreshed from Google Patents.
EP0251880A2
Expired / Lapsed
EP
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Reduction in power rail perturbation and in the effect thereof on integrated circuit performance
Assignee: Fairchild Semiconductor Corp
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Filing: 1987-06-23
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Granted: —
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Expires: 2007-06-23
Abstract
Abstract To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extend to the dambars at the sides of the leadframe. An additional lead is obtained from a conductive element originating near the paddle and supported by one of the two lead frame rails.
Inventors
- 👤 Dana Fraser
- 👤 Ray Mentzer
- 👤 Jerry Gray
- 👤 Geoff Hannington
- 👤 Susan Keown
- 👤 Gaetan L. Mathieu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 20:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00353; H03K19/0175; H03K19/018; H03K19/01806; H10; H10W; H10W44/00; H10W44/501; H10W70/00; H10W70/40; H10W70/421; H10W72/00; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
102 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first power rail of a given type; a second device stage having a second power rail of the same type as said first power rail and isolated from said first power rail; a first lead having one end coupled to said first power rail; a second lead having one end coupled to said second power rail; and means for coupling the respective other ends of said first and second leads to one another, for coupling thereby said first and second leads to an external power line.
Claim 2
Dependent Claim
102 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first power rail of a given type; a second device stage having a second power rail of the same type as said first power rail and isolated from said first power rail; a first lead having one end coupled to said first power rail; a second lead having one end coupled to said second power rail; and means for coupling the respective other ends of said first and second leads to one another, for coupling thereby said first and second leads to an external power line.
Claim 3
Dependent Claim
15 words
An apparatus as in claim 1, wherein the inductance of said coupling means is minimized.
Claim 4
Dependent Claim
24 words
An apparatus as in claim 2, wherein said first lead, said second lead, and said coupling means are of a continuously integral metallic material.
Claim 5
Dependent Claim
19 words
An apparatus as in claim 1, wherein said first lead, said second lead, and said coupling means are integral.
Claim 6
Dependent Claim
24 words
An apparatus as in claim 4, wherein said first lead, said second lead, and said coupling means are of a continuously integral metallic material.
Claim 7
Dependent Claim
98 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first power rail of a given type; a second device stage having a second power rail of the same type as said first power rail and isolated from said first power rail; a first lead having one end connected to said first power rail; and a second lead having one end connected to said second power rail; said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to an external power line.
Claim 8
Dependent Claim
98 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first power rail of a given type; a second device stage having a second power rail of the same type as said first power rail and isolated from said first power rail; a first lead having one end connected to said first power rail; and a second lead having one end connected to said second power rail; said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to an external power line.
Claim 9
Dependent Claim
23 words
An apparatus as in claim 6, further comprising a pin continuously integral with said first and second leads at the merged ends thereof.
Claim 10
Dependent Claim
33 words
An apparatus as in claim 6, wherein said first and second leads are merged at the respective other ends thereof to form a common segment, the inductance of said common segment being minimized.
Claim 11
Dependent Claim
16 words
An apparatus as in claim 8, further comprising a pin continuously integral with said common segment.
Claim 12
Dependent Claim
32 words
An apparatus as in claim 9, wherein said first power rail is a ground rail, said second power rail is a ground rail, and said external power line is an external ground.
Claim 13
Dependent Claim
35 words
An apparatus as in claim 9, wherein said first power rail is a V cc rail, said second power rail is a V cc rail, and said external power line is a V cc line.
Claim 14
Dependent Claim
74 words
A lead configuration for an integrated circuit, comprising: a first lead having one end adapted for connection to a bonding pad of said integrated circuit; a second lead having one end adapted for connection to another bonding pad of said integrated circuit, said first and second leads being merged at the respective other ends thereof; and means for coupling said first and second leads through the merged ends thereof to an external power line.
Claim 15
Dependent Claim
74 words
A lead configuration for an integrated circuit, comprising: a first lead having one end adapted for connection to a bonding pad of said integrated circuit; a second lead having one end adapted for connection to another bonding pad of said integrated circuit, said first and second leads being merged at the respective other ends thereof; and means for coupling said first and second leads through the merged ends thereof to an external power line.
Claim 16
Dependent Claim
24 words
A lead configuration as in claim 12, further comprising a pin continuously integral with said first and second leads at the merged ends thereof.
Claim 17
Dependent Claim
34 words
A lead configuration as in claim 12, wherein said first and second leads are merged at the respective other ends thereof to form a common segment, the inductance of said common segment being minimized.
Claim 18
Dependent Claim
17 words
A lead configuration as in claim 14, further comprising a pin continuously integral with said common segment.
Claim 19
Dependent Claim
82 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first ground rail; a second device stage having a second ground rail isolated from said first ground rail; afirst lead having one end connected to said first ground rail; and a second lead having one end connected to said second ground rail; said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to an external ground.
Claim 20
Dependent Claim
82 words
Apparatus for reducing ground bounce in an integrated circuit, comprising: a first device stage having a first ground rail; a second device stage having a second ground rail isolated from said first ground rail; afirst lead having one end connected to said first ground rail; and a second lead having one end connected to said second ground rail; said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to an external ground.
Claim 21
Dependent Claim
24 words
An apparatus as in claim 16, further comprising a dynamic ground reference changer connected between said first device stage and said second device stage.
Claim 22
Dependent Claim
22 words
An apparatus as in claim 16, wherein said first device stage comprises input circuitry and said second device stage comprises output circuitry.
Claim 23
Dependent Claim
22 words
An apparatus as in claim 16, wherein said first device stage comprises TTL/ECL circuitry, and said second device stage comprises ECL circuitry.
Claim 24
Dependent Claim
90 words
An apparatus as in claim 16 wherein said first device stage includes a first V cc rail and said second device stage includes a second V cc rail isolated from said first V cc rail, further comprising: a third lead having one end connected to said first V cc rail; and a fourth lead having one end connected to said second V cc rail; said third and fourth leads being merged at the respective other ends thereof for coupling said third and fourth leads to an external V cc line.
Claim 25
Dependent Claim
213 words
An octal registered integrated circuit transceiver having reducing ground bounce effect, comprising: a latch having IV cc and IGND power rails; an output buffer comprising an input circuit coupled to the output of said latch and having said IV cc rail in common with said latch; a phase splitter circuit coupled to said input circuit and having said lv cc in common with said latch ; an output circuit coupled to said phase splitter circuit and having an isolated OV cc rail and an isolated OGND rail; an AC Miller killer circuit coupled to said output circuit; and a DC Miller killer circuit coupled to said output circuit; a ground lead configuration comprising a first lead having one end connected to said IGND rail; and a second lead having one end connected to said OGND rail, said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to external ground; and aV cc lead configuration comprising a third lead having one end connected to said IV cc rail; and a fourth lead having one end connected to said OV cc rail, said third and fourth leads being merged at the respective other ends thereof for coupling said third and fourth leads to external Vcc.
Claim 26
Dependent Claim
213 words
An octal registered integrated circuit transceiver having reducing ground bounce effect, comprising: a latch having IV cc and IGND power rails; an output buffer comprising an input circuit coupled to the output of said latch and having said IV cc rail in common with said latch; a phase splitter circuit coupled to said input circuit and having said lv cc in common with said latch ; an output circuit coupled to said phase splitter circuit and having an isolated OV cc rail and an isolated OGND rail; an AC Miller killer circuit coupled to said output circuit; and a DC Miller killer circuit coupled to said output circuit; a ground lead configuration comprising a first lead having one end connected to said IGND rail; and a second lead having one end connected to said OGND rail, said first and second leads being merged at the respective other ends thereof for coupling said first and second leads to external ground; and aV cc lead configuration comprising a third lead having one end connected to said IV cc rail; and a fourth lead having one end connected to said OV cc rail, said third and fourth leads being merged at the respective other ends thereof for coupling said third and fourth leads to external Vcc.
Claim 27
Dependent Claim
37 words
An octal registered transceiver as in claim 21, further comprising a dynamic ground reference circuit coupled to said latch and said output buffer for improving the noise margin at the interface of said latch and output buffer.
Claim 28
Dependent Claim
110 words
A leadframe for PDIP integrated circuit packages, comprising: a paddle; a plurality of leads originating near said paddle and terminating in two parallel rows of pins; first and second dambars integrally connected to said leads in proximity to and parallel to said respective rows of pins; first and second parallel rails, the ends of said dambars being connected to respective rails and normal thereto; first and second paddle support bars integrally connected to respective dambars and to respective opposite sides of said paddle nearest said dambars, said paddle support bars being located between leads; and an additional lead originating near said paddle and integrally connected to one of said rails.
Claim 29
Dependent Claim
110 words
A leadframe for PDIP integrated circuit packages, comprising: a paddle; a plurality of leads originating near said paddle and terminating in two parallel rows of pins; first and second dambars integrally connected to said leads in proximity to and parallel to said respective rows of pins; first and second parallel rails, the ends of said dambars being connected to respective rails and normal thereto; first and second paddle support bars integrally connected to respective dambars and to respective opposite sides of said paddle nearest said dambars, said paddle support bars being located between leads; and an additional lead originating near said paddle and integrally connected to one of said rails.
Claim 30
Dependent Claim
20 words
A leadframe as in claim 23, wherein said additional lead is merged with one of said leads at a pin.
Claim 31
Dependent Claim
164 words
An integrated circuit output buffer having an input circuit, and output circuit having an output pulldown transistor, and a DC miller killer circuit, said DC Miller killer circuit comprising: a first transistor for discharging charge coupled through the Miller capacitance of said output pulldown transistor; a first resistor connected between the collector of said first transistor and the base of said output pulldown transistor, the value of said first resistor being selected to limit the discharge rate of said output pulldown transistor; a second transistor for switching said first transistor in response to an output enable signal; at least one diode connected between the collector of said second transistor and the base of said first transistor, the number of diodes being selected to delay the turn-on of said first transistor; and an alternate discharge path including a resistor and a diode connected in series between the base of said first transistor and ground, for discharging stored charge from the base of said first transistor.
Claim 32
Dependent Claim
164 words
An integrated circuit output buffer having an input circuit, and output circuit having an output pulldown transistor, and a DC miller killer circuit, said DC Miller killer circuit comprising: a first transistor for discharging charge coupled through the Miller capacitance of said output pulldown transistor; a first resistor connected between the collector of said first transistor and the base of said output pulldown transistor, the value of said first resistor being selected to limit the discharge rate of said output pulldown transistor; a second transistor for switching said first transistor in response to an output enable signal; at least one diode connected between the collector of said second transistor and the base of said first transistor, the number of diodes being selected to delay the turn-on of said first transistor; and an alternate discharge path including a resistor and a diode connected in series between the base of said first transistor and ground, for discharging stored charge from the base of said first transistor.
Claim 33
Dependent Claim
38 words
An output buffer as in claim 25, wherein a V cc power rail coupled to said input circuit and said DC Miller killer circuit is isolated from a V c c power rail coupled to said output circuit.
References Cited (Backward Citations)
No citation records indexed.
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