EP0251506A1
Expired / Lapsed
EP
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Process for producing a double diffused MOS transistor structure
Assignee: Vishay Siliconix Inc
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Filing: 1987-06-03
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Granted: —
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Expires: 2007-06-03
Abstract
Abstract In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.
Inventors
- 👤 Adrian I. Cogan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 16:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10P; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
A process of fabricating a double diffused metal oxide semiconductor transistor structure characterized by the steps of: sequentially forming on a semiconductor substrate (10) a thin film (12) of gate oxide, a layer (14) of polysilicon, and a layer (16) of thermal oxide; etching a window through the layers and the thin film so that the polysilicon layer is configured into gate regions (14A,14B) having side walls; implanting nitrogen in the semiconductor substrate window region for forming an oxidation inhibitor to silicon; depositing silicon oxide (22,24) over the side walls of the gate regions; depositing silicon nitride over the silicon oxide; implanting P+ and P- semiconductor type material through the window between the gate regions; growing an oxide plug (24) over the implanted P+ region; and implanting N-type material to form a junction adjacent to the gate regions.
Claim 2
Dependent Claim
138 words
A process of fabricating a double diffused metal oxide semiconductor transistor structure characterized by the steps of: sequentially forming on a semiconductor substrate (10) a thin film (12) of gate oxide, a layer (14) of polysilicon, and a layer (16) of thermal oxide; etching a window through the layers and the thin film so that the polysilicon layer is configured into gate regions (14A,14B) having side walls; implanting nitrogen in the semiconductor substrate window region for forming an oxidation inhibitor to silicon; depositing silicon oxide (22,24) over the side walls of the gate regions; depositing silicon nitride over the silicon oxide; implanting P+ and P- semiconductor type material through the window between the gate regions; growing an oxide plug (24) over the implanted P+ region; and implanting N-type material to form a junction adjacent to the gate regions.
Claim 3
Dependent Claim
17 words
A process as claimed in claim 1 characterized by the step of forming metal contact regions (33).
Claim 4
Dependent Claim
19 words
A process as claimed in claim 1 or 2, characterized by the step of removing the oxide plug (34).
Claim 5
Dependent Claim
23 words
A process as claimed in claim 1, 2 or 3 characterized by the step of depositing a passivation layer (36) over the structure.
Claim 6
Dependent Claim
23 words
A process as claimed in claim 1, 2, 3 or 4 characterized by the step of forming bonding pads to the gate regions.
Claim 7
Dependent Claim
21 words
A process as claimed in claim 1, 2, 3, 4 or 5 characterized in that only five masking steps are employed.
References Cited (Backward Citations)
EP0097866A2
Cited
US4466176A
Cited
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