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EP0097866A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of fabricating a semiconductor device with a base region having a deep portion

Assignee: General Electric Co
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Filing: 1983-06-14
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Granted: —
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Expires: 2003-06-14
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Abstract

Abstract @ A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P + base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N + region through the third window. The P-N junction between the N + region and the deep P + base region terminates at the surface of the wafer. The second oxide layer is removed, exposing the P-N junction, and the wafer is metallized, thereby implementing an electrical short across the P-N junction.

Inventors

  • 👤 Bantval Jayant Baliga
  • 👤 Michael Stuart Adler

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 11:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/411; H10D12/441; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10P; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S257/00; Y10S257/914

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 267 words
A process of fabricating a semiconductor device with a base region having a deep portion, comprising the steps of: (a) forming an insulating layer on the upper surface of a wafer of semiconductor material comprised of a substrate with a layer of one dopant type thereon; (b) forming a refractory electrode layer on the upper surface of the insulating layer; (c) opening a first window through the refractory electrode layer; (d) forming a first mask layer at least in the first window and opening a second window in the first mask layer. the second window being located within the first window; (e) diffusing into the wafer through the second window a first region of the opposite dopant type and of predetermined depth; (f) forming a second mask layer selectively located within the second window; (g) selectively removing the first mask layer, thereby opening a third window defined by the first window and the second mask layer located within the first window; (h) diffusing into the wafer through the third window a second region of the same dopant type as the first region but of lesser depth; (i) diffusing into the wafer through the third window a third region of the one dopant type and of lesser depth than the second region, the P-N junction thus-formed between the first and third regions terminating at the upper surface of the wafer beneath the second mask layer; (j) removing the second mask layer; and (k) metallizing the semiconductor material exposed as a result of removing the second mask layer, the metallization thereby implementing an electrical short across the P-N junction.
Claim 2
Dependent Claim 267 words
A process of fabricating a semiconductor device with a base region having a deep portion, comprising the steps of: (a) forming an insulating layer on the upper surface of a wafer of semiconductor material comprised of a substrate with a layer of one dopant type thereon; (b) forming a refractory electrode layer on the upper surface of the insulating layer; (c) opening a first window through the refractory electrode layer; (d) forming a first mask layer at least in the first window and opening a second window in the first mask layer. the second window being located within the first window; (e) diffusing into the wafer through the second window a first region of the opposite dopant type and of predetermined depth; (f) forming a second mask layer selectively located within the second window; (g) selectively removing the first mask layer, thereby opening a third window defined by the first window and the second mask layer located within the first window; (h) diffusing into the wafer through the third window a second region of the same dopant type as the first region but of lesser depth; (i) diffusing into the wafer through the third window a third region of the one dopant type and of lesser depth than the second region, the P-N junction thus-formed between the first and third regions terminating at the upper surface of the wafer beneath the second mask layer; (j) removing the second mask layer; and (k) metallizing the semiconductor material exposed as a result of removing the second mask layer, the metallization thereby implementing an electrical short across the P-N junction.
Claim 3
Dependent Claim 14 words
The invention according to claim 1 wherein the first mask layer comprises silicon nitride.
Claim 4
Dependent Claim 31 words
The invention according to claim 2 wherein the step of forming the silicon nitride first mask layer comprises low pressure chemical vapor deposition of a reaction product of silane and ammonia.
Claim 5
Dependent Claim 25 words
The invention according to claim 1 wherein the step of forming the second mask layer comprises growing the layer by thermal oxidation of wafer material.
Claim 6
Dependent Claim 14 words
The invention according to claim 1 wherein the semiconductor device comprises a MOSFET .
Claim 7
Dependent Claim 15 words
The invention according to claim 1 wherein the semiconductor device comprises an insulated gate rectifier.
Claim 8
Dependent Claim 22 words
The invention according to claim 1 wherein the one dopant type is N type and the opposite dopant type is P type.
Claim 9
Dependent Claim 12 words
The invention according to claim 7 wherein the semiconductor material comprises silicon.
Claim 10
Dependent Claim 25 words
The invention according to claim 8 wherein the step of forming the second mask layer comprises growing the layer by thermal oxidation of wafer material.

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