Patent EP0250171B1 successfully refreshed from Google Patents.
EP0250171B1
Expired / Lapsed
EP
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Compound semiconductor devices
Assignee: Massachusetts Institute of Technology
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Filing: 1987-06-12
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Granted: 1992-11-11
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Expires: 2007-06-12
Abstract
Abstract Monolithic integration of Si MOSFETs (10) and gallium arsenide MESFETs (100) on a silicon substrate (12) is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers (14 to 17) of SiO2 and Si3N4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs (100) are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si3N4/SiO2 layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.
Inventors
- 👤 Hong Kyun Choi
- 👤 Bor-Yeu Tsaur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 18:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/08; H10D84/0123; H10D84/0126; H10D84/0158; H10D86/00; H10D86/01; H10D86/03; H10D87/00; H10H; H10H29/00; H10H29/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/072; Y10S148/097; Y10S148/149; Y10S438/00; Y10S438/973
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
272 words
A method of fabricating compound semiconductor devices (210) of III-V or II-VI material and semiconductor devices (200) of silicon on a common substrate of a first conductivity type with low resistance interconnections between the compound semiconductor devices and the silicon devices formed in the substrate comprising the steps of: (a) forming Si devices (200) having regions of a second conductivity type opposite to said first conductivity type (34'/30'/32') and wherein one of said regions (32') extends laterally along the planar surface of the substrate; (b) forming a protective layer (16'/17') over the Si devices and the remainder of said substrate surface; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate, a portion of the perimeter of one of said openings being coextensive with said extended region, the substrate region underlying said opening being heavily doped to form a low resistance region (50) of said second conductivity type extending to the planar surface of the substrate in contact with the extended region; (d) forming a layer (54) of said compound semiconductor on the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices (56/58/60/62) having junctions formed of second conductivity type regions on the remaining single crystalline compound semiconductor (54) with the low resistance region (50) contacting said extended region 32' of said Si devices to form said low resistance interconnection in said substrate; and (g) forming ohmic contacts (72, 70, 28') on said devices (200, 210).
Claim 2
Dependent Claim
24 words
A method as claimed in claim 1, characterised in that the low resistance region (50) is formed before the protective layer (16'/17') is formed.
Claim 3
Dependent Claim
24 words
A method as claimed in claim 1, characterised in that the low resistance region is formed during the formation of the compound semiconductor layer.
Claim 4
Independent Claim
27 words
A method as claimed in any preceding claim, characterised in that the substrate comprises a single crystal: silicon, or a silicon on sapphire, or a silicon-on-insulator substrate.
Claim 5
Independent Claim
20 words
A method as claimed in any preceding claim, characterised in that the protective layer comprises a layer of SiO₂ (16').
Claim 6
Independent Claim
22 words
A method as claimed in any preceding claim, characterised in that the protective layer comprises layers of SiO₂ (16') and Si₃N₄ (17').
Claim 7
Independent Claim
20 words
A method as claimed in any preceding claim, characterised in that the compound semiconductor is GaAs or an alloy thereof.
Claim 8
Dependent Claim
20 words
A method as claimed in claim 7, characterised in that the gallium arsenide semiconductor device is an optoelectronic device (210).
Claim 9
Independent Claim
20 words
A method as claimed in any preceding claim, characterised in that the Si devices are part of an Si circuit.
Claim 10
Independent Claim
28 words
A method as claimed in any preceding claim, characterised in that the compound semiconductor devices are transistors from the class comprising MESFETs, bipolar transistors, or modulation doped FETs.
Claim 11
Independent Claim
27 words
A method as claimed in any preceding claim, characterised in that the compound semiconductor devices are optoelectronic devices from the class comprising LED, lasers and light detectors.
Claim 12
Independent Claim
26 words
A method as claimed in any preceding claim, characterised in that the compound semiconductor devices are part of a circuit consisting of transistors and optoelectronic devices.
Claim 13
Independent Claim
48 words
A method as claimed in any preceding claim, characterised in that the ohmic contacts for said Si devices and compound semiconductor devices is formed after the compound semiconductor device is formed and the ohmic contacts for the Si devices is formed through openings made in said protective layer.
References Cited (Backward Citations)
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