Patent EP0250078A2 successfully refreshed from Google Patents.
EP0250078A2
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Programmable low impedance interconnect circuit element
Assignee: Microsemi SoC Corp
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Filing: 1987-05-01
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Granted: —
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Expires: 2007-05-01
Abstract
Abstract A programmable interconnect device for use in integrated circuits comprises a first conductive layer (12), an insulating layer (14, 16, 18) over said first conductive layer, and a second conductive layer (20) over said insulating layer. There is described the application of a programming voltage to cause the formation of at least one controlled radius filament formed from at least one of said first or second conductive layers, this may have a resistance of less than 300 Ohms. Suitably, the first conductive layer may be a polysilicon and the insulating layer a silicon nitride. The invention also relates to the method of forming such a circuit element on a substrate in a CMOS or bipolar application process.
Inventors
- 👤 Amr M. Mohsen
- 👤 John L. Mccollum
- 👤 Esmat Z. Hamdy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 13:03
CPC Classifications
H; H10; H10B; H10B20/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
67 words
A programmable low impedance interconnect circuit element, including: a first conductive layer; an insulating layer over said first conductive layer, and a second conductive layer over said insulating layer, wherein the application of a programming voltage causes the formation of at least one controlled radius filament formed from at least one of the said first or second conductive layers having a resistance of less than 300 ohms.
Claim 2
Dependent Claim
67 words
A programmable low impedance interconnect circuit element, including: a first conductive layer; an insulating layer over said first conductive layer, and a second conductive layer over said insulating layer, wherein the application of a programming voltage causes the formation of at least one controlled radius filament formed from at least one of the said first or second conductive layers having a resistance of less than 300 ohms.
Claim 3
Dependent Claim
50 words
A programmable low impedance interconnect circuit element, including: a first conductive layer; an insulating layer over said first conductive layer, said insulating layer having a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second conductive layer over said insulating layer.
Claim 4
Dependent Claim
50 words
A programmable low impedance interconnect circuit element, including: a first conductive layer; an insulating layer over said first conductive layer, said insulating layer having a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second conductive layer over said insulating layer.
Claim 5
Dependent Claim
27 words
The programmable low impedance interconnect circuit element of claim 2 wherein said insulating layer further includes a third silicon dioxide portion over said second silicon nitride portion.
Claim 6
Dependent Claim
49 words
The programmable low impedance interconnect circuit of claim 2 or 3 wherein said insulating layer contains at least one controlled-radius filament of conductive material formed from at least one of said first or second conductive layers extending therethrough and in electrical contact with said first and second conductive layers.
Claim 7
Dependent Claim
31 words
The programmable low impedance interconnect circuit of claim 1, 2, 3 or 4, wherein at least one of said conductive layers is formed of a material having a high electromigration immunity.
Claim 8
Dependent Claim
26 words
The programmable low impedance interconnect circuit of claim 1, 2, 3, 4 or 5, wherein at least one of said conductive layers is heavily doped polysilicon.
Claim 9
Dependent Claim
37 words
The programmable low impedance interconnect circuit of claim 1, 2 or 3, wherein said first conductive layer is a diffusion and wherein said second conductive layer is heavily doped polysilicon having the same polarity as said diffusion.
Claim 10
Dependent Claim
20 words
The programmable low impedance interconnect circuit of claim 7, wherein said second conductive layer is covered by a metal layer.
Claim 11
Dependent Claim
22 words
The programmable low impedance interconnect circuit of claim 1, 2 or 3, wherein said first and second conductive layers are a metal.
Claim 12
Dependent Claim
43 words
The programmable low impedance interconnect circuit of claim 2, wherein said first conductive layer is a diffusion and wherein said second conductive layer is a sandwich of heavily doped polysilicon layer having the same polarity as said diffusion under a metal conductive layer.
Claim 13
Dependent Claim
34 words
A programmable low impedance interconnect circuit element including: a first conductive layer, a silicide layer covering said first conductive layer, an insulating layer covering said silicid layer, a metal layer covering said insulating layer.
Claim 14
Dependent Claim
34 words
A programmable low impedance interconnect circuit element including: a first conductive layer, a silicide layer covering said first conductive layer, an insulating layer covering said silicid layer, a metal layer covering said insulating layer.
Claim 15
Dependent Claim
25 words
The programmable low impedance interconnect circuit element of claim 11, further including a barrier metal layer in between said insulating layer and said metal layer.
Claim 16
Dependent Claim
28 words
The programmable low impedance interconnect circuit element of claim 11, wherein said first conductive layer is a metal or a sandwich of a metal and a barrier metal.
Claim 17
Dependent Claim
21 words
The programmable low impedance interconnect circuit element of claim 11, 12 or 13, wherein said first conductive layer is a polysilicon.
Claim 18
Dependent Claim
23 words
The programmable low impedance interconnect circuit element of any one of claims 11 to 14, wherein said insulating layer is a silicon nitride.
Claim 19
Dependent Claim
47 words
The programmable low impedance interconnect circuit element of any one of claims 11 to 15, wherein said insulating layer contains at least one controlled-radius filament of conductive material extending therethrough and in electrical contact with said silicide layer and said conductive metal or metal with barrier layer.
Claim 20
Independent Claim
125 words
A method of forming a programmable low impedance interconnect circuit element on a substrate in a CMOS fabrication process including the steps of: defining and doping with a first conductivity type, a first region in said substrate for forming the lower electrode of the programmable low impedance circuit interconnect element simultaneous with a definition and doping of the regions for doping source drain regions in said substrate, removing the inital gate oxide layer in said first region, depositing a dielectric layer for said programmable low impedance circuit interconnect element over said region, depositing a conductive layer to form the upper electrode for said programmable low impedance circuit interconnect over said dielectric layer, defining said conductive layer and said dielectric layer, continuing said CMOS process sequence.
Claim 21
Independent Claim
125 words
A method of forming a programmable low impedance interconnect circuit element on a substrate in a CMOS fabrication process including the steps of: defining and doping with a first conductivity type, a first region in said substrate for forming the lower electrode of the programmable low impedance circuit interconnect element simultaneous with a definition and doping of the regions for doping source drain regions in said substrate, removing the inital gate oxide layer in said first region, depositing a dielectric layer for said programmable low impedance circuit interconnect element over said region, depositing a conductive layer to form the upper electrode for said programmable low impedance circuit interconnect over said dielectric layer, defining said conductive layer and said dielectric layer, continuing said CMOS process sequence.
Claim 22
Dependent Claim
28 words
The method of claim 17 wherein the conductive layer to form the upper electrode is fabricated of polysilicon having a conductivity type the same as said first region.
Claim 23
Independent Claim
69 words
A method of forming a programmable low impedance interconnect circuit element in a bipolar fabrication process including the steps of: defining a region in the emitter for use as the lower electrode of the programmable low impedance circuit element, forming a dielectric layer over said defined region, depositing an upper electrode conductor region, defining said upper electrode conductor region and said dielectric region, continuing said bipolar fabrication process sequence.
Claim 24
Independent Claim
69 words
A method of forming a programmable low impedance interconnect circuit element in a bipolar fabrication process including the steps of: defining a region in the emitter for use as the lower electrode of the programmable low impedance circuit element, forming a dielectric layer over said defined region, depositing an upper electrode conductor region, defining said upper electrode conductor region and said dielectric region, continuing said bipolar fabrication process sequence.
Claim 25
Dependent Claim
24 words
The method of claim 19 wherein said upper electrode conductor region is fabricated of polysilicon having a conductivity type the same as said emitter.
References Cited (Backward Citations)
No citation records indexed.
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