Patent EP0249903A2 successfully refreshed from Google Patents.
EP0249903A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1987-06-12
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Granted: —
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Expires: 2007-06-12
Abstract
Abstract A semiconductor memory device includes a main memory cell array (30A), a redundancy memory cell array (30B), bonding pads for receiving an address signal, a row decoder (32) for selecting a row of the main memory cell array (30A), in accordance with the row address signal, and an exchange controller (46) connected to receive the address signal, which is programmable to inhibit the selective operation of the row decoder (32) to select the row of the redundancy memory cell array (32B), in response to specific address signals. The semiconductor memory device further includes bonding pads each for receiving a test signal. The exchange controller (46) is connected to receive the test signal for inhibiting the selective operation of the row decoder (32) and selecting the row of the redundancy memory cell array (30B), in response to the test signal.
Inventors
- 👤 Shinji C/O Patent Division Saito
- 👤 Shigeru C/O Patent Division Atsumi
- 👤 Sumio C/O Patent Division Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 14:43
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
172 words
A semiconductor memory device comprising: a memory unit (30) including a plurality of memory blocks, at least one memory block forming a redundancy memory section (30B), and the remaining memory blocks forming a main memory section (30A); a pad section for receiving an address signal (AR); selection means (32) connected to said pad section, for selecting the memory block of said main memory section (30A), in accordance with the address signal (AR); and exchange control means (46, 60-1 to 60-M, 63, 68), connected to said pad section, which is programmable to inhibit the selective operation of said selection means (32) and to select the memory block of said redundancy memory section (30B), in response to a least one specified address signal; characterized in that said pad section is further provided for receiving a test signal (TEST), and said exchange control means is further provided for inhibiting the selective operation of said selection means (32) and selecting the memory block of said redundancy memory section (30B), in response to the test signal (TEST).
Claim 2
Dependent Claim
172 words
A semiconductor memory device comprising: a memory unit (30) including a plurality of memory blocks, at least one memory block forming a redundancy memory section (30B), and the remaining memory blocks forming a main memory section (30A); a pad section for receiving an address signal (AR); selection means (32) connected to said pad section, for selecting the memory block of said main memory section (30A), in accordance with the address signal (AR); and exchange control means (46, 60-1 to 60-M, 63, 68), connected to said pad section, which is programmable to inhibit the selective operation of said selection means (32) and to select the memory block of said redundancy memory section (30B), in response to a least one specified address signal; characterized in that said pad section is further provided for receiving a test signal (TEST), and said exchange control means is further provided for inhibiting the selective operation of said selection means (32) and selecting the memory block of said redundancy memory section (30B), in response to the test signal (TEST).
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1, characterized in that said memory unit (30) is a matrix array of memory cells (MC) arranged in the form of rows and columns, and each memory block is constitutued by the memory cells (MC) in the same row.
Claim 4
Dependent Claim
42 words
A semiconductor memory device according to claim 1, characterized in that said redundancy memory section (30B) is formed of a single memory block, and said pad section has a bonding pad (PD) serving as an input terminal for the test signal (TEST).
Claim 5
Dependent Claim
71 words
A semiconductor memory device according to claim 3, characterized in that said exchange control means includes a control circuit (54) connected to the bonding pad, for inhibiting the selective operation of said selection means (32) in response to the test signal (TEST), and a drive circuit (52) connected to the bonding pad (PD), for driving the memory block of said redundancy memory section (30B) in response to the test signal (TEST).
Claim 6
Dependent Claim
67 words
A semiconductor memory device according to claim 4, characterized in that said. exchange control means further includes an address detector (50) connected to receive said address signal (AR), which is programmable to detect a specified address signal (AR), each of said control circuit (54) and drive circuit (52) is connected to said address detector (50) to respond to a detection signal supplied from the address detector (50).
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 5, characterized in that said control circuit is a NOR gate (54), and said driving circuit is an OR gate (52).
Claim 8
Dependent Claim
46 words
A semiconductor memory device according to claim 1, characterized in that said redundancy memory section (30B) is formed of a plurality of memory blocks, and said pad section has a plurality of bonding pads (PDi) each serving as an input terminal for the test signal (TEST)>
Claim 9
Dependent Claim
78 words
A semiconductor memory device according to claim 7, characterized in that said exchange control means includes a control circuit (54) connected to said bonding pads (PDi), for inhibiting the selective operation of said selection means (32) in response to the test signal (TEST), and a plurality of drive circuits (52-1 to 52-M) respectively connected to said bonding pads (PDi), for driving the respective memory blocks of said redundancy memory section (30B) in response to the test signal (TEST).
Claim 10
Dependent Claim
107 words
A semiconductor memory device according to claim 8, characterized in that said exchange control means further includes a plurality of address detectors (50-1 to 50-M) connected to receive said address signal (AR), each of which is programmable to detect a specified address signal, said control circuit (54) is connected to the address detectors (50-1 to 50-M) to respond to a detection signal supplied from one of said address detectors (50-1 to 50-M), and said drive circuits (52-1 to 52-M) are connected to the respective address detectors (50-1 to 50-M) to respond to a detection signal supplied from the associated one of said address detectors (50-1 to 50-M).
Claim 11
Dependent Claim
29 words
A semiconductor memory device according to claim 9, characterized in that said control circuit is a NOR gate (54), and said drive circuits are OR gates (52-1 to 52-M).
Claim 12
Dependent Claim
63 words
A semiconductor memory device according to claim 1, characterized in that said pad section includes at least one bonding pad (PDi) serving as an input terminal for the test signal (TEST), and characterized by further comprising potential setting means (Ri) for causing said at least one bonding pad (PDi) to be set at a predetermined potential when no test signal (TEST) is supplied.
Claim 13
Dependent Claim
35 words
A semiconductor memory device according to claim 11, characterized in that said potential setting means includes resistive means (Ri) formed between a bonding pad (PDi) and one of source and ground potential terminals (VCC, VSS).
Claim 14
Dependent Claim
65 words
A semiconductor memory device according to claim 1, characterized in that said redundancy memory section (30B) is formed of a plurality of memory blocks, and said pad section has a first bonding pad (PD) serving as an input terminal for the test signal and a plurality of second bonding pads serving as an input port for the address signal (AR) and a test address signal.
Claim 15
Dependent Claim
131 words
A semiconductor memory device according to claim 13, characterized in that said exchange control means includes decoder means (60-1 to 60-4) connected to said first and second bonding pads, for decoding the test address signal in response to said test signal (TEST) to generate an internal test signal (TEST) from one of output terminals thereof, a control circuit (54) connected to the output terminals of said decoding means (60-1 to 60-4), for inhibiting the selective operation of said selection means (32) in response to the internal test signal (TEST), and a plurality of drive circuits (52-1 to 52-4) respectively connected to the output terminals of said decoder means (60-1 to 60-4), for driving the respective memory blocks of said redundancy memory section (30B) in response to the internal test signal (TEST).
Claim 16
Dependent Claim
107 words
A semiconductor memory device according to claim 14, characterized in that said exchange control means further includes a plurality of address detectors (50-1 to 50-4) connected to receive said address signal (AR), each of which is programmable to detect a specified address signal, said control circuit (54) is connected to the address detectors (50-1 to 50-4) to respond to a detection signal supplied from one of said address detectors (50-1 to 50-4), and said drive circuits (52-1 to 52-4) are connected to the respective address detectors (50-1 to 50-4) to respond to a detection signal supplied from the associated one of said address detectors (50-1 to 50-4).
Claim 17
Dependent Claim
78 words
A semiconductor memory device according to claim 14, characterized in that said first bonding pad is set at one of first, second, and third level potentials to further serve as an input terminal for another signal of first and second level potentials, said decoder means is connected to said first bonding pad through a test signal detector (63, 68) for detecting that a third level potential is applied to the first bonding pad as said test signal (TEST).
References Cited (Backward Citations)
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