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EP0249548A2
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Dual-port semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1987-06-05
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Granted: —
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Expires: 2007-06-05
Abstract
Abstract In a dual-port semiconductor memory device, one serial memory cell (SC1, SC2,...) of a serial access memory (25) is provided for a predetermined number of bit line pairs (BL1- BL1 , BL2- BL2 ; BL3- BL3 , BL4- BL4 ;...), and a transfer gate circuit (23, 24) is provided between the serial memory cell and the predetermined number of bit line pairs so that only one bit line pair is selectively coupled to the one serial memory cell at one time. An access to the dual-port semiconductor memory device is made in n/m stages when there are n bit line pairs and m serial memory cells (MC) in the serial access memory.
Inventors
- 👤 Hiroshi Nagayama
- 👤 Fumio Baba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
377 words
A dual-port semiconductor memory device comprising: a row address decorder (18) supplied with a row address for decoding the row address; a column address decoder (19) supplied with a column address for decoding the column address; a memory cell array (21) comprising an array of memory cells (MC), each of the memory cells being coupled to one of a plurality of bit lines (BL1, BL1 BL2, BL2 ., BLn, BLn ) and to one of a plurality of word lines (WL1, WL2,...,WLk), said bit lines constituting n bit line pairs, where n is an integer, said row address decoder selecting a specific word line responsive to a decoded output of said row address decoder; a first transfer gate means (20) coupled to said n bit line pairs for selecting at least one of said n bit line pairs responsive to a decoded output of said column address decoder (19); a first pair of data buses (DB, DB ) coupled to said n bit line pairs via said first transfer gate means (20); a first port (41) coupled to said first pair of data buses; sense amplifier means (22) for sensing and amplifying a potential difference between two bit lines in each of said n bit line pairs; second transfer gate means (23, 24) coupled to said sense amplifier means; serial access memory means (25) coupled to said second transfer gate means, said second transfer gate means (23, 24) selectively coupling n/m bit line pair groups to said serial access memory means via said sense amplifier means in n/m sequential stages, where m is an integer smaller than n and each of said n/m bit line pair groups are constituted by m different bit line pairs; third transfer gate means (26, 27) coupled to said serial access memory means (25); a second pair of data buses (SDB, SDB ) coupled to said serial access memory means (25) via said third transfer gate means (26), said third transfer gate means sequentially coupling the m bit line pairs in each bit line pair group to second pair of data buses in each of the n/m stages via said sense amplifier means and said second transfer gate means; and a second port (42) coupled to said second pair of data buses.
Claim 2
Dependent Claim
377 words
A dual-port semiconductor memory device comprising: a row address decorder (18) supplied with a row address for decoding the row address; a column address decoder (19) supplied with a column address for decoding the column address; a memory cell array (21) comprising an array of memory cells (MC), each of the memory cells being coupled to one of a plurality of bit lines (BL1, BL1 BL2, BL2 ., BLn, BLn ) and to one of a plurality of word lines (WL1, WL2,...,WLk), said bit lines constituting n bit line pairs, where n is an integer, said row address decoder selecting a specific word line responsive to a decoded output of said row address decoder; a first transfer gate means (20) coupled to said n bit line pairs for selecting at least one of said n bit line pairs responsive to a decoded output of said column address decoder (19); a first pair of data buses (DB, DB ) coupled to said n bit line pairs via said first transfer gate means (20); a first port (41) coupled to said first pair of data buses; sense amplifier means (22) for sensing and amplifying a potential difference between two bit lines in each of said n bit line pairs; second transfer gate means (23, 24) coupled to said sense amplifier means; serial access memory means (25) coupled to said second transfer gate means, said second transfer gate means (23, 24) selectively coupling n/m bit line pair groups to said serial access memory means via said sense amplifier means in n/m sequential stages, where m is an integer smaller than n and each of said n/m bit line pair groups are constituted by m different bit line pairs; third transfer gate means (26, 27) coupled to said serial access memory means (25); a second pair of data buses (SDB, SDB ) coupled to said serial access memory means (25) via said third transfer gate means (26), said third transfer gate means sequentially coupling the m bit line pairs in each bit line pair group to second pair of data buses in each of the n/m stages via said sense amplifier means and said second transfer gate means; and a second port (42) coupled to said second pair of data buses.
Claim 3
Dependent Claim
66 words
A dual-port semiconductor memory device as claimed in claim 1, characterized in that said serial access memory means (25) comprises m serial memory cells (SC1, SC2,..., SCm), each of said m serial memory cells being coupled to corresponding ones of bit line pairs in each of the n/m bit line pair groups via said second transfer gate means (23, 24) and said sense amplifier means (22).
Claim 4
Dependent Claim
66 words
A dual-port semiconductor memory device as claimed in any one of claims 1 and 2, characterized in that said second transfer gate means comprises n/m transfer gate circuits (23, 24), each of said n/m transfer gate circuits comprising m gates for coupling the m bit line pairs in one bit line pair group to said serial access memory means (25) via said sense amplifier means (22).
Claim 5
Dependent Claim
80 words
A dual-port semiconductor memory device as claimed in any one of claims 1 to 3, characterized in that said third transfer gate means comprises a pointer register (27) and a transfer gate circuit (26) comprising m gates for coupling the m bit line pairs in each bit line pair group to said second pair of data buses (SDB, SDB ) in each of the n/m stages, said m gates being sequentially opened by an output of said pointer register (27).
Claim 6
Dependent Claim
50 words
A dual-port semiconductor memory device as claimed in claim 4, characterized in that said pointer register (27) enters a predetermined m-bit data which is successively shifted, said m gates of said second transfer gate means being supplied with an m-bit parallel output of said pointer register and opened sequentially thereby.
Claim 7
Dependent Claim
135 words
A dual-port semiconductor memory device as claimed in any one of claims 1 to 5, characterized in that it further comprises a counter (11) for counting a shift clock and a transfer control signal generator (12) for generating n/m transfer control signals responsive to an output of said counter, said second transfer gate means (23, 24) coupling one of the n/m bit line pair groups to said serial access memory means (25) via said sense amplifier means (22) in each of the n/m stages responsive to one of said n/m transfer control signals, said third transfer gate means (26, 27) sequentially coupling the m bit line pairs in each bit line pair group to said second pair of data buses (SDB, S DB ) in each of the n/m stages responsive to said shift clock.
Claim 8
Dependent Claim
92 words
A dual-port semiconductor memory device as claimed in claim 6, characterized in that said second transfer gate means comprises n/m transfer gate circuits (23, 24), each of said n/m transfer gate circuits comprising m gates for coupling the m bit line pairs in one bit line pair group to said serial access memory means (25) via said sense amplifier means (22), said transfer control signal generator (12) generating a transfer control signal for opening one of said n/m transfer gate circuits every time a counted value in said counter (11) reaches m.
References Cited (Backward Citations)
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