Block electrically erasable eeprom

Abstract

Abstract An electrically programmable, electrically erasable floating gate memory cell comprises a semiconductor substrate material (10) with implanted source (20) and drain (30) regions; a floating gate (60) electrically insulated from the semiconductor substrate material extends over a portion of drain region and over a portion of the semiconductor substrate material between the drain region and the source region. A control gate (90), electrically insulated from the floating gate and from the semiconductor substrate material, lies above the floating gate and the semiconductor substrate material. The control gate extends from the drain region to the source region so that the control gate, as far as it overlaps the floating gate, forms a control gate of a floating gate device and, to the extent that it extends beyond the floating gate over a portion of the source region, further forms the control gate of a select transistor device of an EEPROM memory cell. A grounding means is provided for grounding and floating the select transistor for programming and erasing the cell as required.

Inventors

• 👤 Gheorghe Samachisa
• 👤 Chien-Sheng Su
• 👤 George Smarandoiu
• 👤 Ting-Wah Wong

Bibliographic Details