Abstract A semiconductor nonvolatile memory device includes: a plurality (30) of nonvolatile random access memory cells each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell, a sense circuit (13) for sensing a level of potential of a power source (Vcc) and, based on the sensed level, selecting a store operation or a recall operation, and a first terminal (11) for the power source and a second terminal (12) for an auxiliary power source (V aux ). The detection of a rise or fall of the potential (Vcc) at the first terminal (11) is carried out in the sense circuit (13) and based on the result of the potential detection, a data transmission from the volatile random access memory cell to the nonvolatile erasable programmable read only memory cell or from the nonvolatile erasable programmable read only memory to the volatile random access memory is automatically carried out.
A semiconductor nonvolatile memory device comprising: a plurality of nonvolatile random access memory cells, each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell; sense circuit means operable to sense a level of potential of a power source, and based on a sensed level, to select a store operation or a recall operation; and a first terminal means for receiving a power source voltage and a second terminal means for receiving an auxiliary power source voltage; wherein, in use, detection of a rise or fall of a potential at said.first terminal means is carried out in said sense circuit means, and based on a result of said potential detection, a data transmission from a volatile random access memory cell to a nonvolatile erasable programmable read only memory cell or from a nonvolatile erasable programmable read only memory cell to a volatile random access memory cell is automatically carried out.
Claim 2
Dependent Claim
155 words
A semiconductor nonvolatile memory device comprising: a plurality of nonvolatile random access memory cells, each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell; sense circuit means operable to sense a level of potential of a power source, and based on a sensed level, to select a store operation or a recall operation; and a first terminal means for receiving a power source voltage and a second terminal means for receiving an auxiliary power source voltage; wherein, in use, detection of a rise or fall of a potential at said.first terminal means is carried out in said sense circuit means, and based on a result of said potential detection, a data transmission from a volatile random access memory cell to a nonvolatile erasable programmable read only memory cell or from a nonvolatile erasable programmable read only memory cell to a volatile random access memory cell is automatically carried out.
Claim 3
Dependent Claim
19 words
A device according to claim 1, wherein said sense circuit means is a positive side Vcc voltage sense circuit.
Claim 4
Dependent Claim
34 words
A device according to claim 2, wherein said positive side Vcc voltage sense circuit comprises a pair of voltage divider circuits each constituted by a pair of depletion type MOS transistors, and respective buffers.
Claim 5
Dependent Claim
31 words
A device according to claim 1, 2, or 3, wherein said volatile memory cell is an SRAM cell, and said nonvolatile erasable programmable read only memory cell is an EEPROM cell.
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