§
Luxuse
Patent Intelligence
Sign In
Patent US539730A successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0247739A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor nonvolatile memory device

Assignee: Fujitsu Ltd
•
Filing: 1987-04-30
•
Granted: —
•
Expires: 2007-04-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor nonvolatile memory device includes: a plurality (30) of nonvolatile random access memory cells each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell, a sense circuit (13) for sensing a level of potential of a power source (Vcc) and, based on the sensed level, selecting a store operation or a recall operation, and a first terminal (11) for the power source and a second terminal (12) for an auxiliary power source (V aux ). The detection of a rise or fall of the potential (Vcc) at the first terminal (11) is carried out in the sense circuit (13) and based on the result of the potential detection, a data transmission from the volatile random access memory cell to the nonvolatile erasable programmable read only memory cell or from the nonvolatile erasable programmable read only memory to the volatile random access memory is automatically carried out.

Inventors

  • 👤 Hideki Arakawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 22:23
CPC Classifications
G; G11; G11C; G11C17/00; G11C14/00; G11C14/0054; G11C14/0063; G11C5/00; G11C5/14; G11C5/141; G11C5/143

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 155 words
A semiconductor nonvolatile memory device comprising: a plurality of nonvolatile random access memory cells, each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell; sense circuit means operable to sense a level of potential of a power source, and based on a sensed level, to select a store operation or a recall operation; and a first terminal means for receiving a power source voltage and a second terminal means for receiving an auxiliary power source voltage; wherein, in use, detection of a rise or fall of a potential at said.first terminal means is carried out in said sense circuit means, and based on a result of said potential detection, a data transmission from a volatile random access memory cell to a nonvolatile erasable programmable read only memory cell or from a nonvolatile erasable programmable read only memory cell to a volatile random access memory cell is automatically carried out.
Claim 2
Dependent Claim 155 words
A semiconductor nonvolatile memory device comprising: a plurality of nonvolatile random access memory cells, each constituted by a volatile memory cell and a nonvolatile erasable programmable read only memory cell; sense circuit means operable to sense a level of potential of a power source, and based on a sensed level, to select a store operation or a recall operation; and a first terminal means for receiving a power source voltage and a second terminal means for receiving an auxiliary power source voltage; wherein, in use, detection of a rise or fall of a potential at said.first terminal means is carried out in said sense circuit means, and based on a result of said potential detection, a data transmission from a volatile random access memory cell to a nonvolatile erasable programmable read only memory cell or from a nonvolatile erasable programmable read only memory cell to a volatile random access memory cell is automatically carried out.
Claim 3
Dependent Claim 19 words
A device according to claim 1, wherein said sense circuit means is a positive side Vcc voltage sense circuit.
Claim 4
Dependent Claim 34 words
A device according to claim 2, wherein said positive side Vcc voltage sense circuit comprises a pair of voltage divider circuits each constituted by a pair of depletion type MOS transistors, and respective buffers.
Claim 5
Dependent Claim 31 words
A device according to claim 1, 2, or 3, wherein said volatile memory cell is an SRAM cell, and said nonvolatile erasable programmable read only memory cell is an EEPROM cell.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag