Method for automated optical inspection of printed circuits

Claim 2

Optical inspection method for the automated detection of fatal faults in printed circuits wherein the said printed circuits are scanned by an optical scanner, and the scanner supplies a binary representation of the features at the surface of the printed circuit being inspected, characterized in that the said binary representation, or a pre-processed version thereof, is subjected to a local component labeling process in data scanning order, that during said component labeling an information is gathered on-the-fly at a rate corresponding to the data acquisition rate, and which information establishes whether an arbitrary pair of points on the printed circuit under inspection belongs to the same conductive entity, and wherein, at the same time, global labels which are computed in certain pre-chosen check points are analyzed for the existence of conductive connections between them, the detected connections being compared with the precomputed correct connections between corresponding check points stored in a reference list, with any miscorrespondence indicating a fatal fault.

Claim 3

Method in accordance with claim 1, characterized in that the comparison is carried out by establishing a correspondence between global labels in check points of a certain type and pre-computed reference global labels in corresponding points, and that the global labels of other check points are compared with corresponding ones of the reference, and that any miscorrespondence indicates a defect of the 'open circuit' type, while any merge event between different global labels indicates a defect of the 'short circuit' type.

Claim 4

Method in accordance with claim 1, characterized in that the component labeling is performed by assigning, to each current picture element, a label bit equal either to a corresponding label bit of one of the immediate neighbors of this picture element, or equal to zero, or to a corresponding bit of a new, still unused label, the decision depending on the type of the 3×3 neighborhood of the current picture element, this type being defined by a single processing element which maps the neighborhood of the current picture element into a new bit number, the latter being used to control those processing elements that perform the labeling, and to control the channel connecting the labeling processing element with a microprocessor which compares the resulting connectivity information with the reference list.

Claim 5

Method in accordance with claim 1, characterized in that in parallel with said local component labeling process a random access memory (RAM1) is filled with flags at addresses equal to labels, said flags indicating active labels used in the current data row, that the contents of two further random access memories ries (RAM2, RAM3) are sequentially analyzed for the occurrence of a label which was active two rows ago, and which became inactive one row ago, the value of such a released label being loaded into a first-in/first-out buffer the output signal of which serves as a new label for component labeling, said value of a released label being optionally transferred to a microprocessor for keeping track of the active labels.

Claim 6

Method in accordance with claim 4, characterized in that said random access memory (RAM1) is filled with flags only at such label addresses which correspond to start events, when the label has just been taken from said first-in/first-out buffer, as well as for those types of 3×3 neighborhoods of a current picture element for which the label is equal to the label of an immediate neighbor in the preceding row.

Claim 7

Method in accordance with claim 1, characterized in that either the image of a scanned printed circuit, or its preprocessed version is skeletonized by thinning, conserving a 4-connectivity such that there do not exist skeleton points with more than four external connections, said special points being 0-, 1-, 3-, and 4-joints, and those 2-joints in which a start-new-label event or a merge-two-label event occurs, and being described in terms of their 3×3 neighborhood which is mapped into a few-bit output signal representing type and control signals for the generation of a message to be transferred to a microprocessor.

Claim 8

Method in accordance with claim 6, characterized in that a stage for one pixel 4-connectivity thinning consists of three processing elements, two of which are fed in parallel by the output of the third one, that the latter labels internal pixels of a conductive entity image representation, and that the two other processing elements classify each pixel in accordance with a pattern of its 3×3 vicinity and a pattern of internal points in its 3*3 vicinity, a pixel being deleted if both classifications coincide.

Claim 9

Method in accordance with claim 6, characterized in that prior to a skeletonizing and a component labeling operation, an image representation of a scanned printed circuit undergoes a modification by a horizontal edge smoothing processing element which maps 10-bit input consisting of a 3×3 neighborhood of a current pixel and an additional bit to a two-bit output, one of the output bits being used as an additional input bit for the next pixel to be processed, and that a logical function of a processing element is defined in a way conserving the connectivity of the image.

Claim 10

Method in accordance with claim 6, characterized in that for enabling the connectivity analysis of multi-connected patterns, a skeletonized image is subjected to the deletion of certain special points, including 3-joints, and 4-joints, and non-skeleton points, that the information on deleted points, with the exception of their labels, is transferred to a microprocessor which tries to match these points to vertices of a pre-computed graph representation of the skeletonized reference, that at the same time local component labeling is performed on disconnected pieces of the skeletonized image, wherein the information on disconnected special points of the skeletonized image, namely on terminal points, 'start' events and 'merge' events, may include their local labels, that said microprocessor uses those of the special points for which there exists no match in the reference, as regular points, in particular for local label merging, keeping track of each skeletonized conductive entity, including information on the number of times this entity intersects a current row, that the reference is represented as a graph with a list of vertices and their connections by simple edges, such that the information in the microprocessor enables the comparison of this graph representation with a graph representation of a skeletonized printed circuit image, where any miscorrespondence indicates a defect, and a delay in a decision on a defect being less than a constant number of rows, enabling on-the-fly defect data documentation.

Claim 11

Method in accordance with claim 9, characterized by marking special points to be deleted from a skeleton together with their immediate skeleton neighbors, and also marking skeleton neighbors of already marked points, and repeating this marking operation several times, and by removing each time, except for the last time, marked points from the disconnected skeleton and producing, as a result, two separate binary representations of a skeletonized image, one containing disconnected skeleton pieces, the other containing vicinities of deleted points, viz. knots, while disconnected skeleton edges have common points with some knot in their terminal points, a knotted image being subjected to an auxiliary local component labeling, and further characterized in that additional information on mergers and starts of auxiliary labels is transferred to a microprocessor, while a disconnected skeleton is being subjected to the usual local component labeling and, in addition, auxiliary labels are being transferred to the microprocessor in terminal points of disconnected pieces.

Claim 12

Method in accordance with claim 10, characterized in that the marking for special points is done alternately for special 2-joints and 3-/4-joints in such a way that knots, originating from 2-joints and 3-/4-joints never merge together.

Claim 13

Method in accordance with claim 1, characterized in that images of scanned printed circuits are preprocessed considering predefined tolerances for minimum conductor width and for minimum acceptable interwire gap width, by narrowing/broadening conductive entities in such a way that the output image representation either is narrowed to about one half of the minimum acceptable conductor width, causing a disconnection in places of too narrow wires, or is broadened to about one half of the minimum acceptable gap width, causing a short circuit in places of too narrow gaps.

Claim 14

Method in accordance with claim 12, characterized in that at least two identical channels are fed in parallel with the binary image representation, both channels containing a preprocessor with a number of processing elements sufficient to cover the maximum number of narrowing/broadening operations, the processing elements receiving two additional input bits enabling the choice of one of at least three programs, viz. for narrowing, for broadening, and for a unity operation which leaves the input unchanged, the distribution of these control signals enabling the narrowing/broadening operations in accordance with said predetermined tolerances, and the analysis of the narrowed/broadened images simultaneously through a comparison of their connectivity attributes with pre-computed connectivity attributes of correspondingly narrowed/broadened references.

Claim 15

Method in accordance with claim 13, characterized in that three identical channels are in parallel fed with the binary image representation, two channels being programmed for different numbers of narrowing, including identity, the third channel being programmed for broadening, each channel comparing the connectivity attributes against correspondingly prepared reference connectivity attributes.

Claim 16

Method in accordance with claim 13, characterized in that the binary image representation is split by a transformation block into two possibly complementary images, one of which containing only connectivity type patterns, and the other one containing only large area patterns, that the first binary image representation is fed into a connectivity testing block for testing by comparison of its connectivity attributes with corresponding connectivity attributes of the reference, and that the second binary image representation fed into a reference comparison scheme which either works idle for an inspected printed circuit with only narrow line patterns, or which provides on-the-fly data alignment and comparison with the pre-computed reference of only large areas, and which produces an indication of care/don't care regions on those large areas.

Claim 17

Method in accordance with claim 15, characterized in that said transformation block performs a narrowing operation on a number of picture elements larger than corresponds to the maximum acceptable line width, and that the resulting supernarrowed binary image representation is subtracted from an appropriately delayed original image representation, the ensuing difference containing only connectivity pattern to be tested, while the supernarrowed image representation contains only large areas to be checked by the reference comparison scheme.

Claim 18

Method in accordance with claim 15, characterized in that for enabling a testing of either an average line width or an average conductor density, an additional arithmetic channel is fed in parallel with said logical connectivity checking channels with either of said two image representations, that this arithmetic channel comprises a preprocessor, a preaverager and a decimator, the output of which is hooked to an attached microprocessor, that said preprocessor converts a binary image representation into a few-bit output data stream, wherein each data item is a result either of a distance transformation or of a neighbor number counting operation, and that said preaverager performs a weighted averages in each N×N pixel block and transfers the result to a microprocessor which accomplishes an averaging by recursive filtering of incoming data and compares the results with a given nominal value within given tolerances.

Claim 19

Method in accordance with claim 17, characterized in that for enabling a distance transformation, said preprocessor of the arithmetic channel comprises a few lines of cascade-connected processing elements, the first cascade line including processing elements with 1-bit input and 2-bit output, which are controlled for choosing either a sequence of different narrowing operations or a sequence of nearest neighbor values, other cascaded lines of processing elements serving to delay a few-bit intermediate result which equals a sum of a result kept in a previous stage and an output bit of a corresponding stage of said first cascade, the summation being performed by a look-up table adder, whereas a few-bit result of the last stage may be set to zero for all non-skeletal pixels.

Claim 20

Method in accordance with claim 1, characterized in that registration of detected data check points is performed by matching them to corresponding reference check points and by simultaneous computation of coefficients of a geometrical transformation between the reference and the inspected data in the vicinity of the current scanning line, a detected transformation being used as well for partial reordering of the reference check points and/or for recomputation of data check point coordinates.

Claim 21

Method in accordance with claim 19, characterized in that the inspection is performed at a number of overlapping strips each strip being compared by a conductivity analysis with a slightly narrower reference strip, while the computed geometrical transformation is used in addition for computing two points which correspond to the two edges of the reference strip, and that at least one subsequent data line is set to zero outside the interval between the said points, thus providing processing of only the data described by the current strip of the reference.

Claim 22

Method in accordance with claim 17, characterized in that conductivity testing includes the computation of a geometric transformation between a scanned printed circuit and its reference and the use of transformation coefficients in the computation of dynamic offsets for the reference or optical data in a reference comparison subsystem, said dynamic offsets being used for the dynamic alignment of at least one subsequent reference or optical data row in the reference comparison subsystem.

Claim 23

Method in accordance with claim 9, characterized in that an input image representation is broadened and processed in parallel by a distance transformer to create an image of different weights, each weight corresponding to an actual line width and given tolerances, including the smallest weight for those picture elements which are not conductive and which belong to the broadened input image, that said image of weights is set to zero outside the skeletons of the broadened as well as the original input, that the received weighted skeleton is processed by a special point detector which includes the detection of points where the weight changes, and wherein the information on special points includes weight values in terminal points of skeleton segments, said information being transferred to the second-level microprocessor which treats this information as a graph representation of a skeletonized image with certain weights on each edge, and which compares this information with the reference graph representation that includes nominal weights on each edge of the reference graph, and that a predetermined relation between the reference and said weight values is tested, whereby an 'open circuit' error is indicated when a data edge has a smaller weight than the corresponding reference edge relating to a too narrow line, and optionally a 'too wide line' error is indicated when a data edge has a greater weight than the corresponding reference edge, a 'hard open circuit' is indicated when the data edge does not exist, a 'short circuit' error is indicated when there are extraneous connections of the smallest weight, relating to a too narrow gap, and a 'hard short circuit' is indicated when there are extraneous connections of any weight other than the smallest.

Claim 24

Apparatus for the automated optical inspection of printed circuits having an optical front end and processing facilities, characterized in that said optical front end (1) comprises an optical scanner (6) designed for linewise scanning of the printed circuit under investigation and for supplying, at its output line (7), a data stream arranged in the order of scanning, said output line (7) being connected to one input of a first look-up table (8) the second input of which is connected to a reference source (11, 12, 15), of an at least two-bit signal, and the output of which is hooked up to a transformation unit (9) which in turn is connected to a second look-up table (10) which interfaces with a general conductivity analysis subsystem (3) comprising special purpose hardware (16), signal processors (16, 17) and a local host computer (14), and with a comparator (13).

Claim 25

Apparatus for the automated optical inspection of printed circuits having an optical front end and processing facilities, characterized in that said optical front end (1) comprises an optical scanner (6) designed for linewise scanning of the printed circuit under investigation and for supplying, at its output line (7), a data stream arranged in the order of scanning, said output line (7) being connected to one input of a first look-up table (8) the second input of which is connected to a reference source (11, 12, 15), of an at least two-bit signal, and the output of which is hooked up to a transformation unit (9) which in turn is connected to a second look-up table (10) which interfaces with a general conductivity analysis subsystem (3) comprising special purpose hardware (16), signal processors (16, 17) and a local host computer (14), and with a comparator (13).

Claim 26

Apparatus in accordance with claim 23, characterized in that said special purpose hardware (16) comprises parallel and cascade interconnection of elementary recursive processing elements with possible logical functions between them, that each processing element maps a 3×3 neighborhood of a current pixel to a few-bit output, wherein several pixels of said 3×3 neighborhood may be fed by previously computed values of one of the output bits.