Patent EP0246125A2 successfully refreshed from Google Patents.
EP0246125A2
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Translinear static memory cell with bipolar and mos devices
Assignee: Fairchild Semiconductor Corp
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Filing: 1987-04-16
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Granted: —
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Expires: 2007-04-16
Abstract
Abstract A translinear static memory cell employs both bipolar and metal-oxide-semiconductor technologies. Bipolar transistors are employed as switching devices, whereas MOS transistors provide power supply and coupling functions. Among other advantages, the bipolar transistors provide large changes in output current for small changes in input voltage, thereby enabling high level read signals to be obtained. The MOS load and coupling transistors facilitate bidirectional current flow into and out of the cell, thereby enabling write operations to be achieved during relatively short periods of time.
Inventors
- 👤 Raymond A. Heald
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
98 words
A memory cell, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors each having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors.
Claim 2
Dependent Claim
98 words
A memory cell, comprising: a first access line; a pair of second access lines; a pair of cross-coupled bipolar transistors wherein the base of each transistor is connected to the collector of the other transistor and the emitters of the two transistors are connected in common; and a pair of field-effect transistors each having its gate connected to said first access line, one of its source and drain connected to a respective one of said second access lines and the other of its source and drain connected to the base of a respective one of said bipolar transistors.
Claim 3
Dependent Claim
20 words
The memory cell of claim 1 wherein said bipolar transistors are of opposite conductivity type than said MO S transistors.
Claim 4
Dependent Claim
37 words
The memory cell of claim 2 wherein said bipolar transistors are NPN transistors and said field-effect transistors are p-channel MOSFETS having their sources connected to the respective bit lines and their drains connected to the respective bases.
Claim 5
Dependent Claim
30 words
The memory cell of claim 1 wherein said transistors are embodied in a monolithic integrated circuit and said pair of MOS transistors are disposed above said pair of bipolar transistors.
Claim 6
Dependent Claim
40 words
The memory cell of claim 4 wherein said bipolar transistors are connected to one another and said MOS transistors are respectively connected to bipolar transistors by means of a conducting layer sandwiched between said MOS transistors and said bipolar transistors.
Claim 7
Dependent Claim
16 words
The memory cell of claim 5 wherein said conducting layer is comprised of a silicided polysilicon.
Claim 8
Dependent Claim
21 words
The memory cell of claim 6 wherein said MOS transistors are formed in a recrystallized polysilicon layer within said integrated circuit.
Claim 9
Dependent Claim
129 words
A memory circuit, comprising: a matrix of memory cells arranged in a plurality of rows and columns, each cell including a pair of cross-coupled bipolar transistors and a pair of MOS transistors each having one of its source and drain connected to the base of a respective one of said bipolar transistors; a plurality of word lines respectively associated with the rows of memory cells, each word line being connected to the gate terminals of both MOS transistors in each memory cell of an associated row of cells; and a pair of bit lines for each column of memory cells, each of the bit lines being connected to the other of the source and drain of a respective one of the MOS transistors in each cell in the column.
Claim 10
Dependent Claim
129 words
A memory circuit, comprising: a matrix of memory cells arranged in a plurality of rows and columns, each cell including a pair of cross-coupled bipolar transistors and a pair of MOS transistors each having one of its source and drain connected to the base of a respective one of said bipolar transistors; a plurality of word lines respectively associated with the rows of memory cells, each word line being connected to the gate terminals of both MOS transistors in each memory cell of an associated row of cells; and a pair of bit lines for each column of memory cells, each of the bit lines being connected to the other of the source and drain of a respective one of the MOS transistors in each cell in the column.
Claim 11
Dependent Claim
21 words
The memory circuit of claim 8 further including means for applying a substantially constant voltage to each of said bit lines.
Claim 12
Dependent Claim
19 words
The memory circuit of claim 9 further including means for sensing the current in each of said bit lines.
Claim 13
Dependent Claim
39 words
The memory circuit of claim 9 further including means for selectively altering the voltage of one bit line of a pair of bit lines to thereby drain the current from a particular memory cell in a column of cells.
Claim 14
Dependent Claim
56 words
The memory circuit of claim 11 further including means for increasing the conductivity of the MOS transistors in the row of memory cells in which said particular memory cell is located while decreasing the conductivity of the MOS transistors in the other rows during the time that the voltage of said bit line is selectively altered.
Claim 15
Dependent Claim
55 words
The memory circuit of claim 8 wherein said bipolar transistors are NPN transistors each having its base coupled to the collector of the other bipolar transistor in a cell, and said MOS transistors are p-channel devices having their source terminals connected to said bit lines and their drain terminals connected to said bipolar transistors, respectively.
Claim 16
Dependent Claim
22 words
The memory cell of claim 1 including a further access line that is connected to the common emitters of said bipolar transistors.
Claim 17
Dependent Claim
49 words
The memory circuit of claim 8 further including a second plurality of word lines respectively associated with the rows of memory cells, each word line in said second plurality of word lines being connected to the cross-coupled bipolar transistors in each memory cell of an associated row of cells.
Claim 18
Dependent Claim
41 words
The memory circuit of claim 15 wherein the two cross-coupled bipolar transistors in each memory cell have emitter terminals that are connected in common and wherein the word lines in said second plurality of word lines are connected to said emitters.
Claim 19
Dependent Claim
42 words
The memory circuit of claim 8 further including a plurality of auxiliary select lines respectively associated with the columns of memory cells, each select line being connected to the cross-coupled bipolar transistors in each memory cell of an associated column of cells.
Claim 20
Dependent Claim
34 words
The memory circuit of claim 17 wherein the two cross-coupled bipolar transistors in each memory cell have emitter terminals that are connected in common, and wherein said select lines are connected to said emitters.
References Cited (Backward Citations)
No citation records indexed.
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