EP0244628A1 — Sense amplifier for a semiconductor memory device

Claim 1

Independent Claim 206 words

A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor (22), operating as a memory cell, whose control gate is connected to a word line; a first MOS transistor (23), operating as a transfer gate for selecting said first floating gate transistor (22), the gate of said first MOS transistor (23) being connected to a column-select line; a first load (24), connected to the first MOS transistor (23); a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to a first power terminal (Vcc); a second MOS transistor (31), operating as a transfer gate for selecting said second floating gate transistor (32), the gate of said second MOS transistor (31) being connected to a second power terminal (Vpp), for supplying a high potential which is higher than the power voltage from said first power terminal (Vcc); a second load (28), connected to said second MOS transistor (31); and potential-difference detecting means (20), whose first input terminal is connected to the connection point of said first load (24) and said first MOS transistor (27), and whose second input terminal is connected to the connection point of the second load (28) and the second MOS transistor (31).

Claim 2

Dependent Claim 206 words

A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor (22), operating as a memory cell, whose control gate is connected to a word line; a first MOS transistor (23), operating as a transfer gate for selecting said first floating gate transistor (22), the gate of said first MOS transistor (23) being connected to a column-select line; a first load (24), connected to the first MOS transistor (23); a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to a first power terminal (Vcc); a second MOS transistor (31), operating as a transfer gate for selecting said second floating gate transistor (32), the gate of said second MOS transistor (31) being connected to a second power terminal (Vpp), for supplying a high potential which is higher than the power voltage from said first power terminal (Vcc); a second load (28), connected to said second MOS transistor (31); and potential-difference detecting means (20), whose first input terminal is connected to the connection point of said first load (24) and said first MOS transistor (27), and whose second input terminal is connected to the connection point of the second load (28) and the second MOS transistor (31).

Claim 3

Dependent Claim 83 words

A sense amplifier for a semiconductor memory device according to claim 1, further characterized by means (39, 40, 41, 44) for applying, in a data-write mode, the high potential from said second power terminal (Vpp) to the gate of said second MOS transistor (31), and for supplying a signal corresponding to a potential at the second power terminal (Vpp), to the gates of said first MOS transistor (23) and said first floating gate transistor (22), via the word line and the column-select line.

Claim 4

Dependent Claim 36 words

A sense amplifier for a semiconductor memory device according to claim 1, characterized in that the potential at the connection point of said second load (28) and said second MOS transistor (32) is a constant potential.

Claim 5

Dependent Claim 201 words

A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor operating (22) as a memory cell, whose control gate is connected to the word line, and to which is applied a potential corresponding to that at a second power terminal (Vpp), for supplying a potential higher than the power voltage supplied from a first power terminal (Vcc), the control gate of said first floating gate transistor being connected to the word line; a first load (24), connected to said first MOS transistor; a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to said first power terminal (Vcc); a second MOS transistor (31), operating as a transfer gate for selecting said second floating gate transistor (32), the gate of said second MOS transistor (32) being connected to the second power terminal (Vpp); a second load (28), connected to said second MOS transistor (31); and a differential amplifier (26) whose first input terminal is connected to the connection point of said first load (24) and said first MOS transistor (22), and whose second input terminal is connected to the connection point of said second load (28) and second MOS transistor (32).

Claim 6

Dependent Claim 201 words

A sense amplifier for a semiconductor memory device, characterized by a first floating gate transistor operating (22) as a memory cell, whose control gate is connected to the word line, and to which is applied a potential corresponding to that at a second power terminal (Vpp), for supplying a potential higher than the power voltage supplied from a first power terminal (Vcc), the control gate of said first floating gate transistor being connected to the word line; a first load (24), connected to said first MOS transistor; a second floating gate transistor (31), operating as a dummy cell, whose control gate is connected to said first power terminal (Vcc); a second MOS transistor (31), operating as a transfer gate for selecting said second floating gate transistor (32), the gate of said second MOS transistor (32) being connected to the second power terminal (Vpp); a second load (28), connected to said second MOS transistor (31); and a differential amplifier (26) whose first input terminal is connected to the connection point of said first load (24) and said first MOS transistor (22), and whose second input terminal is connected to the connection point of said second load (28) and second MOS transistor (32).

Claim 7

Dependent Claim 72 words

A sense amplifier for a semiconductor memory device according to claim 4, characterized in that, when a shift in the threshold voltage of said first floating gate transistor (22) is monitored, the potential corresponding to that at said second power terminal (Vpp) is gradually increased, and, upon a change in the level of the data stored in said first floating gate transistor (22), said potential is detected by said differential amplifier (27).

Claim 8

Dependent Claim 31 words

A sense amplifier for a semiconductor memory device according to claim 4, further characterized by means (46) for gradually increasing the potential corresponding to that at said second power terminal (Vpp).

Claim 9

Dependent Claim 73 words

A sense amplifier for a semiconductor memory device according to claim 4, characterized in that said second load (28) includes first and second load elements (28A and 28B), said first load element (28A) being turned off when the shift in the threshold voltage of said first floating transistor (22) is monitored, and said second load element (28B) being connected to said second MOS transistor (32), in parallel with said first load element (28A).

Claim 10

Dependent Claim 54 words

A sense amplifier for a semiconductor memory device according to claim 7, characterized in that said first load element (28A) is supplied with the power voltage via a third MOS transistor (30) which is turned off when the amount of shift in the threshold voltage of said first floating gate transistor (22) is monitored.

Claim 11

Dependent Claim 34 words

A sense amplifier for a semiconductor memory device according to claim 7, characterized in that said first load (24) and said second load element (28B) of said second load have the same electrical characteristics.

Claim 12

Dependent Claim 36 words

A sense amplifier for a semiconductor memory device according to claim 4, characterized in that the potential at the connection point of said second load (28) and the second MOS transistor (32) is a constant potential.

Sense amplifier for a semiconductor memory device

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