Patent EP0243235A2 successfully refreshed from Google Patents.
EP0243235A2
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EP
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Noise pulse suppressing circuit in a digital system
Assignee: Fujitsu Ltd
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Filing: 1987-04-10
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Granted: —
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Expires: 2007-04-10
Abstract
Abstract A latch circuit (16) receives and latches an input signal (b) in response to a triggering signal (k) and provides an output signal (c). A counter circuit (13) formed a plurality of D-type flip-flops (12, 14) receives a clock signal (a o ) and produces the triggering signal (k) when a predetermined number of trailing or leading edges of clock pulses have been counted. A logic circuit (11) is connected to the latch circuit (16) for generating a reset signal (h) which is applied to the counter circuit to reset same when the latch circuit output and the input signal have the same logic state and for making the counter circuit active when the latch circuit output and the input signal have complementary logic states. No level change in the output signal will occur if the duration of a level change in the input signal is not sufficient to allow the counter circuit to count the predetermined number of edges of clock pulses; thus enabling the suppression of noise pulses of either positive or negative polarity in the input signal and the production of an output signal having edges synchronized on leading or trailing edges of the clock signal.
Inventors
- 👤 Masato Abe
- 👤 Fumitaka Asami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 18:43
CPC Classifications
H; H03; H03H; H03H17/00; H03K; H03K5/00; H03K5/125; H03K5/1252; H03K3/00; H03K3/02; H03K3/04; H03K3/05; H03K3/06; H03K3/12; H03K3/13
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
1 . A noise pulse suppressing circuit for suppressing noise pulses superposed on an input signal having a binary state, and outputting an output signal responsive to the binary state of the input signal without said noise pulses, said noise pulse suppressing circuit being characterized in that it comprises: a latch circuit (16) for receiving and latching the input signal (b) in response to a triggering signal (k), and outputting the output signal (c), a counter circuit (13) connected to the latch circuit (16) and receiving a clock signal (a o ) for generating the triggering signal at the instant when a predetermined number of pulse edges in the clock signal has been counted, and a logic circuit (11) connected to the latch circuit (16) and to the counter circuit (13) for generating a reset signal (h), which is applied to the counter circuit to reset same when the latch circuit output and the input signal have the same logic state, and for making the counter circuit active when the latch circuit output and the input signal have complementary logic states.
Claim 2
Dependent Claim
181 words
1 . A noise pulse suppressing circuit for suppressing noise pulses superposed on an input signal having a binary state, and outputting an output signal responsive to the binary state of the input signal without said noise pulses, said noise pulse suppressing circuit being characterized in that it comprises: a latch circuit (16) for receiving and latching the input signal (b) in response to a triggering signal (k), and outputting the output signal (c), a counter circuit (13) connected to the latch circuit (16) and receiving a clock signal (a o ) for generating the triggering signal at the instant when a predetermined number of pulse edges in the clock signal has been counted, and a logic circuit (11) connected to the latch circuit (16) and to the counter circuit (13) for generating a reset signal (h), which is applied to the counter circuit to reset same when the latch circuit output and the input signal have the same logic state, and for making the counter circuit active when the latch circuit output and the input signal have complementary logic states.
Claim 3
Dependent Claim
19 words
A noise pulse suppressing circuit according to claim 1, wherein said latch circuit (16) consists of a D-type flip-flop.
Claim 4
Dependent Claim
99 words
A noise pulse suppressing circuit according to any one of claims 1 and 2 wherein said counter circuit comprises a plurality of D-type flip-flops (12, 14; 30, 32, 14) having a data terminal, a clock terminal, a data output terminal, an inverted output terminal and a reset terminal, each with its data input terminal connected to its own inverted output terminal and each inverted output terminal being connected to the clock terminal of the flip-flop in the following stage, except the last stage where the data output terminal is connected to a clock terminal of the latch circuit (16).
Claim 5
Dependent Claim
145 words
A noise pulse suppressing circuit according to claim 3, wherein said logic circuit (11) comprises: a first NAND gate (20) for receiving the output signal (c) from the latch circuit (16) and the input signal in inverted state, a second NAND gate (22) for receiving said input signal (b) and the output signal from the latch circuit in inverted state, a third NAND gate (24) for receiving outputs from the first and second NAND gates and outputting said reset signal (h) which is applied to each reset terminal of the flip-flops of the counter circuit (13), and a fourth NAND gate (10) for receiving said clock signal (a o ) and said reset signal (h) from the third NAND gate, the output signal from the fourth NAND gate being inputted to the clock terminal of the first stage flip-flop (12;30) of the counter circuit (13).
Claim 6
Dependent Claim
156 words
A noise pulse suppressing circuit according to claim 3, wherein said logic circuit (11) comprises: a first NAND gate (20) for receiving the output signal (c) from the latch circuit (16) and the input signal in inverted state, a second NAND gate (22) for receiving said input signal (b) and the output signal from the latch circuit in inverted state, a third NAND gate (24) for receiving outputs from the first and second NAND gates and outputting said reset signal (h) which is applied to each reset terminal of the flip-flops of the counter circuit (13), an inverter (26) for inverting the output signal from said third NAND gate (24), and an OR gate (28) for receiving said clock signal (a o ) and the output signal from the inverter (26), the output signal from the OR gate (28) being inputted to the clock terminal of the first stage flip-flop (12) of said counter circuit (13).
Claim 7
Dependent Claim
54 words
A noise pulse suppressing circuit according to any one of claims 3 to 5, wherein said counter circuit (13) comprises two D-type flip-flops (12, 14), and the output signal is delayed with respect to input signal up to the second trailing edge of the clock signal following a level change of the input signal.
Claim 8
Dependent Claim
55 words
A noise pulse suppressing circuit according to any one of claims 3 to 5, wherein said counter circuit (13) comprises two D-type flip-flops (12, 14), and the output signal is delayed with respect to the input signal up to the second leading edge of the clock signal following a level change of the input signal.
Claim 9
Dependent Claim
56 words
A noise pulse suppressing circuit according to any one of claims 3 to 5, wherein said counter circuit (13) comprises three D-type flip-flops (30, 32, 14), and the output signal is delayed with respect to the input signal up to the fourth trailing edge of the clock signal following a level change of the input signal.
Claim 10
Dependent Claim
53 words
A noise pulse suppressing circuit according to any one of claims 3 to 5, wherein said counter circuit (13) comprises three D-type flip-flops, and the output signal is delayed with respect to the input signal up to the fourth leading edge of the clock signal following a level change of the input signal.
Claim 11
Dependent Claim
56 words
A noise pulse suppressing circuit according to any one of claims 3 to 5, wherein said counter circuit comprises N units of D-type flip-flops connected in cascade, and the output signal is delayed with respect to the input signal up to the 2(N-1)-th edge of the clock signal following a level change in the input signal.
References Cited (Backward Citations)
No citation records indexed.
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