Patent EP0242623A2 successfully refreshed from Google Patents.
EP0242623A2
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EP
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MOS semiconductor device and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1987-03-25
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Granted: —
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Expires: 2007-03-25
Abstract
Abstract In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor (101) is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor (201) is formed in the other element region of the second conductivity type. The complementary MOS transistor (101) is of a surface channel type in which N-and P-channel MOS transistors are respectively formed in a pair of well diffusion layers (34, 35) of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes (41, 42) of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers (34, 35). The double-diffused MOS transistors (201) is of a surface channel type in which a back gate region (45) is formed so as to be self-aligned with the gate electrode (43) and the conductivity type of the gate electrode (43) is different from that of the well diffusion layer (36).
Inventors
- 👤 Koji C/O Patent Division Shirai
- 👤 Ken C/O Patent Division Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 21:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0135; H10D84/0144; H10D84/0165; H10D84/0167; H10D84/0172; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W20/00; H10W20/01; H10W20/031; H10W20/069; Y; Y10; Y10S; Y10S148/00; Y10S148/031; Y10S148/082
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
177 words
A semiconductor device wherein a complementary MOS resistor and a double-diffused MOS transistor are formed in first and second element regions of a second conductivity type formed on a semiconductor substrate of a first conductivity type, comprising: said complementary MOS transistor wherein an N-channel MOS transistor and a P-channel MOS transistor are respectively formed in a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type formed in said first element region of the second conductivity type for said complementary MOS transistor (101); and said double-diffused MOS transistor in which a channel region (45) of the first conductivity type is formed contacting a well diffusion layer (36) of the first conductivity type formed in said second element region of the second conductivity type for said double-diffused MOS transistor (201) and the self-aligned with a gate electrode (43), and source and drain regions (49, 50) of the second conductivity type are formed in the channel region (45) and an element region of the second conductivity type.
Claim 2
Dependent Claim
177 words
A semiconductor device wherein a complementary MOS resistor and a double-diffused MOS transistor are formed in first and second element regions of a second conductivity type formed on a semiconductor substrate of a first conductivity type, comprising: said complementary MOS transistor wherein an N-channel MOS transistor and a P-channel MOS transistor are respectively formed in a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type formed in said first element region of the second conductivity type for said complementary MOS transistor (101); and said double-diffused MOS transistor in which a channel region (45) of the first conductivity type is formed contacting a well diffusion layer (36) of the first conductivity type formed in said second element region of the second conductivity type for said double-diffused MOS transistor (201) and the self-aligned with a gate electrode (43), and source and drain regions (49, 50) of the second conductivity type are formed in the channel region (45) and an element region of the second conductivity type.
Claim 3
Dependent Claim
33 words
A device according to claim 1, wherein conductivity types of the gate electrodes of said N-channel, P-channel, and double-diffused MOS transistors are different from those of respective well diffusion layers (34, 35, 36).
Claim 4
Dependent Claim
29 words
A device according to claim 1, wherein the respective gate electrodes (41, 42, 43) of said N-channel, P-channel, and double-diffused MOS transistors are formed of a polycrystalline silicon layer.
Claim 5
Dependent Claim
17 words
A device according to claim 1, wherein said double-diffused MOS transistor (201) is of a vertical type.
Claim 6
Dependent Claim
173 words
A semiconductor device wherein a complementary MOS transistor and a double-diffused MOS transistor are formed on a semiconductor substrate of a first conductivity type, comprising: at least two first and second r ecesses formed in said semiconductor substrate (57); high concentration buried regions (60, 61) formed on surface of said first and second recesses; first and second element regions (58, 59) of a second conductivity type respectively formed to surround said first and second recesses and having an impurity concentration lower than that of said high concentration buried regions (60, 61); a complementary MOS transistors in which an N-channel MOS transistor and a P-channel MOS transistor are respectively formed in a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type formed in said first element region (58) of the second conductivity type; and a double-diffused MOS transistor in which a channel region (45a) of the first conductivity type is formed so as to be self-aligned with an gate electrode (43a).
Claim 7
Dependent Claim
173 words
A semiconductor device wherein a complementary MOS transistor and a double-diffused MOS transistor are formed on a semiconductor substrate of a first conductivity type, comprising: at least two first and second r ecesses formed in said semiconductor substrate (57); high concentration buried regions (60, 61) formed on surface of said first and second recesses; first and second element regions (58, 59) of a second conductivity type respectively formed to surround said first and second recesses and having an impurity concentration lower than that of said high concentration buried regions (60, 61); a complementary MOS transistors in which an N-channel MOS transistor and a P-channel MOS transistor are respectively formed in a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type formed in said first element region (58) of the second conductivity type; and a double-diffused MOS transistor in which a channel region (45a) of the first conductivity type is formed so as to be self-aligned with an gate electrode (43a).
Claim 8
Dependent Claim
38 words
A device according to claim 5, wherein conductivity types of the respective gate electrodes (41, 42, 43a) of said n-channel, p-channel, and double-diffused MOS transistors are different from those of the respective well diffusion layers, (34, 35, 36a).
Claim 9
Dependent Claim
29 words
A device according to claim 5, wherein the respective gate electrodes (41, 42, 43a) of said N-channel, P-channel, and double-diffused MOS transistors are formed of a polycrystalline silicon layer.
Claim 10
Dependent Claim
17 words
A device according to claim 5, wherein said double-diffused MOS transistor (201) is of a vertical type.
Claim 11
Independent Claim
350 words
A method of manufacturing a semiconductor device in which a complementary MOS transistor (101) and a double-diffused MOS transistor (201) are formed on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first element region of a second conductivity type for said complementary MOS transistor (101) and a second element region of the second conductivity type for said double-diffused MOS transistor (201) on said semiconductor substrate to be electrically isolated from each other; forming a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type in said first element region of the second conductivity type for said complementary MOS transistor (101) and a well diffusion layer (36) of the first conductivity type for compensation of the withstand voltage in said second element region of the second conductivity type for said double-diffused MOS transistor (201); forming undoped gate electrodes (41, 42) in said first well diffusion layer (34) of the first conductivity type and said second well diffusion layer (35) of the second conductivity type for said complementary MOS transistor (101) through a gate oxide film (38) and forming an undoped gate electrode (43) in said second element region of the second conductivity type through said gate oxide film (38); forming a back gate region (45) of the first conductivity type to be self-aligned with said gate electrode (43) formed on said first element region of the first conductivity type for said double-diffused MOS transistor (202); forming source and drain regions (47, 48) of the second conductivity type in said first well diffusion layer (34) of the first conductivity type for said complementary MOS transistor (101) and forming a source region (49) of the second conductivity type in said back gate region (45) and a drain region (50) of the second conductivity type in said second element region of the second conductivity for said double-diffused MOS transistor (201); and forming source and drain regions (53, 54) of the first conductivity type in said second well diffusion layer (35) for said complementary MOS transistors (101).
Claim 12
Independent Claim
350 words
A method of manufacturing a semiconductor device in which a complementary MOS transistor (101) and a double-diffused MOS transistor (201) are formed on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first element region of a second conductivity type for said complementary MOS transistor (101) and a second element region of the second conductivity type for said double-diffused MOS transistor (201) on said semiconductor substrate to be electrically isolated from each other; forming a first well diffusion layer (34) of the first conductivity type and a second well diffusion layer (35) of the second conductivity type in said first element region of the second conductivity type for said complementary MOS transistor (101) and a well diffusion layer (36) of the first conductivity type for compensation of the withstand voltage in said second element region of the second conductivity type for said double-diffused MOS transistor (201); forming undoped gate electrodes (41, 42) in said first well diffusion layer (34) of the first conductivity type and said second well diffusion layer (35) of the second conductivity type for said complementary MOS transistor (101) through a gate oxide film (38) and forming an undoped gate electrode (43) in said second element region of the second conductivity type through said gate oxide film (38); forming a back gate region (45) of the first conductivity type to be self-aligned with said gate electrode (43) formed on said first element region of the first conductivity type for said double-diffused MOS transistor (202); forming source and drain regions (47, 48) of the second conductivity type in said first well diffusion layer (34) of the first conductivity type for said complementary MOS transistor (101) and forming a source region (49) of the second conductivity type in said back gate region (45) and a drain region (50) of the second conductivity type in said second element region of the second conductivity for said double-diffused MOS transistor (201); and forming source and drain regions (53, 54) of the first conductivity type in said second well diffusion layer (35) for said complementary MOS transistors (101).
Claim 13
Dependent Claim
155 words
A method according to claim 9, wherein the step of forming said first well diffusion layer (34) of the first conductivity type and said second well diffusion layer (35) of the second conductivity type in said first element region of the second conductivity typ e for said complementary MOS transistor (101) and forming said well diffusion layer (36) of the first conductivity type for compensation of the withstand voltage in said second element region of the second conductivity type for said double-diffused MOS transistor (201) includes a process of oxidizing surfaces of said first and second element regions of the second conductivity type to form an oxide film (32); selectively removing and opening said oxide film by photolithography; oxidizing said exposed portions of said first and second element regions so as to form a buffer oxide film (33); ion-implanting an impurity of a predetermined conductivity type through said buffer oxide film (33); and then annealing.
Claim 14
Dependent Claim
107 words
A method according to claim 9, wherein the step of forming said gate electrodes (41, 42, 43) for said complementary MOS transistor (101) and said double-diffused MOS transistor (201) includes a process of exposing entire surfaces of said first and second element regions of the second conductivity type for said complementary MOS transistor (101) and said double-diffused MOS transistor (201) and forming a field oxide film (37); selectively removing and opening said field oxide film (37) by photolithography; forming said gate oxide film (38) at the opened portions and depositing a polycrystalline silicon layer (39) on the entire surface; and then patterning said polycrystalline silicon layer (39).
Claim 15
Dependent Claim
89 words
A method according to claim 9, wherein the step of forming said back gate region (45) for said doublediffused MOS transistor (201) includes a process of coating a resist pattern (44) of which a prospective formation portion for said back gate region (45) is opened on the entire surfaces of said first and second element regions; ion-implanting an impurity of the first conductivity type in said second element region of the second conductivity type of said double-diffused MOS transistor (201) through said gate oxide film (38); and then annealing.
Claim 16
Dependent Claim
38 words
A method according to claim 9, wherein an end (43a) at a source region (49) side of said gate electrode (43) of said double-diffused MOS transistor (201) is exposed at the opened portion of said resist pattern (44).
Claim 17
Dependent Claim
136 words
A method according to claim 9, wherein the step of forming source and drain regions (47, 48) in said first well diffusion layer (34) of the first conductivity type for said complementary MOS transistor (201) and forming a source region (4 ) of the second conductivity type in said back gate region (45) for said double-diffused MOS transistor (201) and a drain region (50) of the first conductivity type in said second element region of the second conductivity type includes a process of ion-implanting an impurity of the second conductivity type under the condition in which the gate electrode (42) formed on said first well diffusion layer (34) of the first conductivity type for said complementary MOS transistor (101) and the gate electrode (43) for said double-diffused MOS transistor (201) are exposed; then annealing is performed.
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