Patent EP0241671A2 successfully refreshed from Google Patents.
EP0241671A2
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EP
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Register providing simultaneous reading and writing to multiple ports
Assignee: International Business Machines Corp
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Filing: 1987-02-17
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Granted: —
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Expires: 2007-02-17
Abstract
Abstract A memory cell that allows simultaneous writing into the cell and reading from the cell includes a cross-coupled latch (10) in which two pairs of a load transistor (12, 14) and a pull-down transistor (20, 24) are connected at respective first and second coupling points (16, 18). However, the feedback path from the first coupling point (16) to the gate electrode of the pull-down transistor (24) of the other pair passes through a feedback transistor (30) which can thus selectively open this feedback path. In any access to the memory cell, the feedback path is interrupted. Any one of a plurality of write signals (WP1, WP2) can be impressed upon the gate electrode of the thus separated pull down transistor (24). Simultaneously, the signal on the first coupling point (16) can be selectively impressed upon any combination of a plurality of read lines (58, 60, 62). If a simultaneous writing and reading is being performed, the write signal passes immediately through the memory cell to the read lines.
Inventors
- 👤 Kerry Bernstein
- 👤 Anatol Furman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:40
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
209 words
A memory system comprising: first and second field effect transistors (20, 24), first and second loads (12, 14; 82 84) serially connected to said first and second transistors, respectively, forming a first common point (16) between said first transistor and said first load and a second common point (18) between said second transistor and said second load, said second common point (18) being connected to the control electrode of said first transistor (20), a third field effect transistor (30) connected from said first common point (16) to the gate electrode of said second transistor (24), means for selectively applying a first control voltage (SEL) to the control electrode of said third transistor, a first write line (54), a fourth field effect transistor (40) connected between said first write line and the control electrode of said second transistor (24), means for selectively applying a second control voltage (SP1) to the control electrode of said fourth transistor, a first read line (58), a fifth field effect transistor (48) connected between said read line and said first common point, and means for selectively applying a third control voltage (SP3) to the control electrode of said fifth transistor concurrently with applying said second control voltage to the control electrode of said fourth transistor.
Claim 2
Dependent Claim
209 words
A memory system comprising: first and second field effect transistors (20, 24), first and second loads (12, 14; 82 84) serially connected to said first and second transistors, respectively, forming a first common point (16) between said first transistor and said first load and a second common point (18) between said second transistor and said second load, said second common point (18) being connected to the control electrode of said first transistor (20), a third field effect transistor (30) connected from said first common point (16) to the gate electrode of said second transistor (24), means for selectively applying a first control voltage (SEL) to the control electrode of said third transistor, a first write line (54), a fourth field effect transistor (40) connected between said first write line and the control electrode of said second transistor (24), means for selectively applying a second control voltage (SP1) to the control electrode of said fourth transistor, a first read line (58), a fifth field effect transistor (48) connected between said read line and said first common point, and means for selectively applying a third control voltage (SP3) to the control electrode of said fifth transistor concurrently with applying said second control voltage to the control electrode of said fourth transistor.
Claim 3
Dependent Claim
47 words
A memory system as set forth in Claim 1 wherein: the control voltages applied to the control electrodes of said fourth and fifth transistors (40, 48) are derived from address signals and further including means for applying binary data signals to said first write line (Fig. 4).
Claim 4
Dependent Claim
87 words
A memory system as set forth in Claims 1 or 2 further including: a second write line (56), a sixth field effect transistor (38) connected between said second write line and the control electrode of said second transistor (24), a second read line (60), a seventh field effect transistor (50) connected between said second read line and said first common point (16) and means for applying fourth and fifth control voltages (SP2, SP4) derived from address signals to the control electrodes of said sixth and seventh transistors.
Claim 5
Dependent Claim
33 words
A memory system as set forth in one of the preceding claims wherein said first and second loads are field effect transistors of a different type relative to said first and second transistors.
Claim 6
Dependent Claim
32 words
A memory system as set forth in Claim 4 wherein said loads are depletion-type field effect transistors (12, 14) and said first and second transistors (20, 24) are enhancement-type field effect transistors.
Claim 7
Dependent Claim
32 words
A memory system as set forth in Claim 4 wherein said load field effect transistors (82, 84) are of a conductivity type opposite that of said first and second transistors (20, 24).
Claim 8
Dependent Claim
83 words
A memory system as set forth in one of the preceding claims wherein there are a plurality of sets of said first, second, third, fourth and fifth transistors, first and second loads, first read lines and first write lines, said sets arranged in a register and wherein said means for applying said first, said second and said third control voltages applies said first, said second and said third control voltages to said control electrodes of all said third, fourth and fifth transistors, respectively.
Claim 9
Dependent Claim
58 words
A memory system as recited in one of the preceding claims wherein there are a plurality of sets of said first, second, third, fourth, fifth, sixth and seventh transistors, first and second loads, said sets arranged in an addressable file, and connected to the same first and second read lines and the same first and second write lines.
Claim 10
Dependent Claim
48 words
A memory system as recited in one of the preceding claims wherein there is associated a capacitance (32, 33) effective at the control electrodes of each of said first and second transistors (20, 24) adapted to maintain the previous memory state if there is no further impressed signal.
Claim 11
Dependent Claim
23 words
A memory system as recited in one of the preceding claims wherein said third field effect transistor (30) is made non-conductive during writing.
References Cited (Backward Citations)
No citation records indexed.
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