Pipe-line processing system and microprocessor using the system

Claim 2

A pipe-line processing system using a microprocessor having a single effective address calculating circuit wherein any commands sent from the external device and having a plurality of memory operands respectively are divided into a plurality of inner commands, each having a single memory operand, and the calculation of at least one effective address of one memory operand and the processing of the other operand are performed at the same time.

Claim 3

The pipe-line processing system as claimed in claim l wherein said plurality of memory operands into which the commands sent from the external device is divided are two operands.

Claim 4

The pipe-line processing system as claimed in claim l or claim 2 wherein said inner commands are first and second inner commands, and the processing of the first operand is the reading operation of the first operand from the first effective address.

Claim 5

A microprocessor of the pipe-line processing type, which comprises: decoder means (l) for decoding each of commands sent from external means and for determining if a particular command has a plurality of memory operands; dividing means (3) connected to said decoder means for dividing said command having a plurality of memory operands into a plurality of inner commands each having a single operand respectively; execution means (5) connected to said dividing means for successively executing each inner command thus divided and having a single memory operand; and bus control means (7) connected between said decoder means and said execution means as well as to a bus, for controlling the transfer of information among them.

Claim 6

A microprocessor of the pipe-line processing type, which comprises: decoder means (l) for decoding each of commands sent from external means and for determining if a particular command has a plurality of memory operands; dividing means (3) connected to said decoder means for dividing said command having a plurality of memory operands into a plurality of inner commands each having a single operand respectively; execution means (5) connected to said dividing means for successively executing each inner command thus divided and having a single memory operand; and bus control means (7) connected between said decoder means and said execution means as well as to a bus, for controlling the transfer of information among them.

Claim 7

The microprocessor as claimed in claim 4 wherein said execution means (7) further comprises a single effective address calculating circuit (l0) having a general purpose register (ll) including a plurality of registers, an adder (l3), and a second register (l5), as well as at least first (Q₁) and second (Q₂) stages for placing a first inner command for the first time and then for placing a second inner command, so as to calculate at least first (A) and second (B) effective addresses of the memory operands.

Claim 8

The microprocessor as claimed in claim 4 or 5 wherein said first inner command divided from the command (PUSH DISP (I × 2) sent from the external means is a load command (LD DISP (I × 2)) and said second inner command divided therefrom is a store command (ST (I × l)).

Claim 9

The microprocessor as claimed in claim 5 or 6 wherein when the first inner command is moved to the second stage so as to read one operand from the first effective address, the seond inner command is placed in the first stage so as to calculate the second effective address, thereby permitting the calculation of the second effective address of one operand and the reading-out of the operand from the first effective address at the same time.