Patent EP0240232A2 successfully refreshed from Google Patents.
EP0240232A2
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Digital phase lock loop
Assignee: HP Inc
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Filing: 1987-03-25
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Granted: —
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Expires: 2007-03-25
Abstract
Abstract A digital phase lock loop utilizing a programmable delay line (12) to phase shift the output of a crystal (10) generated reference clock signal and lock it to digitized data transitions recorded on a suitable medium is provided. The output of the delay line (12) is compared to the digitized data transitions in a phase detector (14) to determine if the delay line (12) output leads or lags the data transitions. The delay line (12) is then programmed by an up/down counter circuit (161,163) to reduce the phase difference between the data transition and the delay line (12) output to a minimum value.
Inventors
- 👤 Samuel Howard Gailbreath, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 08:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H04; H04L; H04L7/00; H04L7/0016; H04L7/0033; H04L7/0037; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
A digital phase lock loop for phase locking an output signal to a reference signal said phase lock loop comprising oscillator means (10) for generating said output signal, adjustable phase shift means (12) coupled to the oscillator means (10) for shifting the phase of said output signal with respect to the phase of said reference signal, characterized by phase detector means (14) coupled to said adjustable phase shift means (12) for detecting a phase difference between the output signal and the reference signal and for generating a control signal indicative of said phase difference, and control means (16) coupled to said phase detector means (14) and to said adjustable phase shift means (12), said control means (16) responsive to said control signal to adjust the adjustable phase shift means (12) to shift the phase of said output signal so as to reduce said phase difference between said output signal and said reference signal to a predetermind minimum value.
Claim 2
Dependent Claim
158 words
A digital phase lock loop for phase locking an output signal to a reference signal said phase lock loop comprising oscillator means (10) for generating said output signal, adjustable phase shift means (12) coupled to the oscillator means (10) for shifting the phase of said output signal with respect to the phase of said reference signal, characterized by phase detector means (14) coupled to said adjustable phase shift means (12) for detecting a phase difference between the output signal and the reference signal and for generating a control signal indicative of said phase difference, and control means (16) coupled to said phase detector means (14) and to said adjustable phase shift means (12), said control means (16) responsive to said control signal to adjust the adjustable phase shift means (12) to shift the phase of said output signal so as to reduce said phase difference between said output signal and said reference signal to a predetermind minimum value.
Claim 3
Dependent Claim
35 words
A digital phase lock loop according to Claim 1 characterized in that said adjustable phase shift means (12) comprises a programmable delay line (12) for delaying said output signal for a predetermined period of time.
Claim 4
Dependent Claim
34 words
A digital phase lock loop according to Claim 1 or 2 characterized in that said control means (16) comprises a digital processor (16) responsive to said control signal to program said programmable delay line.
Claim 5
Dependent Claim
46 words
A digital phase lock loop according to Claim 2 or 3 characterized in that said programmable delay line (12) is programmable in discrete predetermind steps to increment or decrement said period of time said output signal is delayed in propagating through said programmable dealy line (12).
Claim 6
Dependent Claim
38 words
A digital phase lock loop according to any of Claims 1,2 or 4 characterized in that said control means (16) comprises an up/down counter circuit (161,163) responsive to said control signal to program said programmable delay line (12).
Claim 7
Dependent Claim
33 words
A digital phase lock loop according to any of claims 1 to 5 characterized in that said control signal is indicative of whether said output signal is leading or lagging said reference signal.
Claim 8
Dependent Claim
39 words
A digital phase lock loop according to any of Claims 1 to 6 characterized in that said digital phase lock loop further comprises filter means (18) coupled to said adjustable phase shift means (12) for filtering said output signal.
Claim 9
Dependent Claim
22 words
A digital phase lock loop according to Claim 7 characterized in that said filter means (18) comprises a phase locked loop (18).
References Cited (Backward Citations)
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