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EP0239937A2
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Serial communications controller
Assignee: Wang Laboratories Inc
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Filing: 1987-03-26
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Granted: —
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Expires: 2007-03-26
Abstract
Abstract A serial communications controller, adapted for transfer of data to memory in a direct memory access interrupt, generates a status word for each frame of data. To allow for uninterrupted transfer of data to memory from frame to frame, the status words are stored in a FIFO along with word counts corresponding to the frames to allow for subsequent identification of the addresses to which the data frames are assigned.
Inventors
- 👤 Teresa Marzucco
- 👤 Patricia A. Martin
- 👤 John Korpusik
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 01:33
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/901; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
Input/output control circuitry for a data communication system for receiving sequential frames of incoming data words and transferring the data words to memory, the control circuitry comprising: means for generating supplemental data to be read from the circuitry for each frame of incoming data; means for counting the number of words within each frame to provide a word count; and means for storing the supplemental data and the associated word counts to permit continued transfer of sequential frames of data and subsequent reading of the supplemental data and word counts from the control circuitry.
Claim 2
Dependent Claim
94 words
Input/output control circuitry for a data communication system for receiving sequential frames of incoming data words and transferring the data words to memory, the control circuitry comprising: means for generating supplemental data to be read from the circuitry for each frame of incoming data; means for counting the number of words within each frame to provide a word count; and means for storing the supplemental data and the associated word counts to permit continued transfer of sequential frames of data and subsequent reading of the supplemental data and word counts from the control circuitry.
Claim 3
Dependent Claim
100 words
Control circuitry for a data communication system for receiving sequential frames of incoming data words and transferring the data words to memory in a direct memory access, the control circuitry comprising: means for providing supplemental data to be read by a central processing unit (CPU) for each frame of incoming data; means for counting the number of words within each frame to provide a word count; and means for storing the supplemental data and the associated word counts to permit continued transfer of sequential frames of data and subsequent reading of the supplemental data and word counts by the CPU.
Claim 4
Dependent Claim
100 words
Control circuitry for a data communication system for receiving sequential frames of incoming data words and transferring the data words to memory in a direct memory access, the control circuitry comprising: means for providing supplemental data to be read by a central processing unit (CPU) for each frame of incoming data; means for counting the number of words within each frame to provide a word count; and means for storing the supplemental data and the associated word counts to permit continued transfer of sequential frames of data and subsequent reading of the supplemental data and word counts by the CPU.
Claim 5
Dependent Claim
22 words
Control circuitry as claimed in claim 1 or 2 wherein the supplemental data may be the status word in an SDLC/HDLC protocol.
Claim 6
Dependent Claim
132 words
A data processing system comprising: a central processing unit (CPU); main memory; a serial communications controller for receiving serial data and converting serial data to parallel bit data for storage in the main memory; and a direct memory access controller for controlling transfer of data from the communications controller; wherein the serial communications controller comprises means for generating status data to be transmitted to the CPU for each frame of incoming serial data, means for counting the number of words in each frame to provide a word count; and means for storing the status data and the associated word counts to permit continued transfer to sequential frames of data under control of the direct memory access controller and to permit subsequent reading of the status data and word counts by the CPU.
Claim 7
Dependent Claim
132 words
A data processing system comprising: a central processing unit (CPU); main memory; a serial communications controller for receiving serial data and converting serial data to parallel bit data for storage in the main memory; and a direct memory access controller for controlling transfer of data from the communications controller; wherein the serial communications controller comprises means for generating status data to be transmitted to the CPU for each frame of incoming serial data, means for counting the number of words in each frame to provide a word count; and means for storing the status data and the associated word counts to permit continued transfer to sequential frames of data under control of the direct memory access controller and to permit subsequent reading of the status data and word counts by the CPU.
Claim 8
Dependent Claim
22 words
Control circuitry as claimed in any of claims 1 to 4, wherein the means for storing comprises a first-in/first-out register (FIFO 42).
Claim 9
Dependent Claim
35 words
Control circuitry as claimed in claim 5, wherein the first-in/first-out register is incremented at the end of each frame and the first-in/first-out is decremented as each word of supplemental data is read by the CPU.
Claim 10
Dependent Claim
22 words
Control circuitry as claimed in any of claims 1 to 6 which is a serial communications controller fabricated on a single chip.
Claim 11
Independent Claim
113 words
A method of transferring sequential frames of incoming words from a communications controller to memory in a direct memory access, the method comprising: generating supplemental data in the communications controller to be read by a central processing unit (CPU) for each frame of incoming words; counting the number of words within each frame to provide a word count; storing the supplemental data and the associated word counts while providing continued transfer of data to memory under direct memory access control; and subsequently reading the supplemental data and word counts by the CPU to establish the memory locations at which the sequential frames of data are stored and to establish the corresponding supplemental data.
Claim 12
Independent Claim
113 words
A method of transferring sequential frames of incoming words from a communications controller to memory in a direct memory access, the method comprising: generating supplemental data in the communications controller to be read by a central processing unit (CPU) for each frame of incoming words; counting the number of words within each frame to provide a word count; storing the supplemental data and the associated word counts while providing continued transfer of data to memory under direct memory access control; and subsequently reading the supplemental data and word counts by the CPU to establish the memory locations at which the sequential frames of data are stored and to establish the corresponding supplemental data.
References Cited (Backward Citations)
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