Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
424 words
I. A buffer circuit comprising: first and second power source terminals and first and second output nodes; a first inverter circuit (23, 26, 29) for receiving an input signal and generating the inverted signal of said input signal from first, second and third output terminals; a second inverter circuit (35, 39) for receiving the signals from said first and third output terminals of said first inverter circuit and generating the inverted signals of these signals from first and second output terminals; first and second bipolar transistors (30, 31) whose bases are commonly connected to the first output terminal of said first inverter circuit (23, 26, 29) and which are connected at one end to the first power source terminal and respectively connected at the other ends to the second and third output terminals of said first inverter circuit; a third bipolar transistor (43) whose base is connected to the first output terminal of said second inverter circuit and which is connected at one end to the first power source terminal and connected at the other end to the second output terminal of said second inverter circuit; first and second bipolar transistor circuits (44, 49 and 32, 53) which are respectively connected between said first power source terminal and the first and second output nodes and are controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second inverter circuit (35, 39) and from the first output terminal of the first inverter circuit (23, 26, 29), respectively; first and second MOS transistors (41 and 47) which are respectively connected between the first and second output nodes and said second power source terminal and are controlled to be set into the opposite conduction states in response to the output signals from the third output terminal of said first inverter circuit (23, 26, 29) and from the second output terminal of said second inverter circuit (35, 39), respectively; and third and fourth MOS transistors (45A and 36A) which are respectively connected between the gates of said first and second MOS transistors (41 and 47) and said second power source terminal and are respectively controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second inverter circuit (35, 39) and from the second output terminal of said first inverter circuit (23, 26,29), wherein output signals in the inversion relation are generated from said first and second output nodes in response to said input signal.
Claim 2
Dependent Claim
42 words
A buffer circuit according to claim 1, characterized in that said first inverter circuit has first to third CMOS inverters (23, 26, and 29) for inverting said input signal and generating output signals from said first to third output terminals thereof, respectively.
Claim 3
Dependent Claim
86 words
A buffer circuit according to claim I or 2, characterized in that said second inverter circuit includes a fourth CMOS inverter (35) for inverting the output signal from the first output terminal of said first inverter circuit (23, 26, 29) and generating an output signal from the first output terminal thereof and a fifth CMOS inverter (39) for inverting the output signal from the third output terminal of said first inverter circuit (23, 26, 29) and generating an output signal from the second output terminal thereof.
Claim 4
Dependent Claim
176 words
A buffer circuit according to claim I, 2, or 3, characterized by further comprising fourth and fifth bipolar transistors (52 and 56) which are respectively connected between the first and second output nodes and the second power source terminal, fifth and sixth MOS transistors (42 and 458) which are respectively connected between the base of said fourth bipolar transistor (52) on one hand and said first output node and the second power source terminal on the other, and seventh and eighth MOS transistors (48 and 36B) which are respectively connected between the base of said fifth bipolar transistor (56) on one hand and said second output node and the second power source terminal on the other, and characterized in that the gates of said fifth to eighth MOS transistors (42, 45B, 48, and 36B) are respectively connected to the third output terminal of said first inverter circuit (23, 26, 29), the first and second output terminals of said second inverter circuit (35, 39), and the second output terminal of said first inverter circuit (23, 26, 29).
Claim 5
Dependent Claim
36 words
A buffer circuit according to any one of claims I to 4, characterized in that each of said first and second bipolar transistor circuits has two bipolar transistors (44, 49 and 32, 53) which are Darlington-connected.