Semiconductor memory device

Claim 1

A semiconductor memory comprising: a plurality of word lines (WL1, WL2); a plurality of pairs of bit lines with a folded bit line structure, each of said plurality of pairs of bit lines being divided into a plurality of blocks (CAL1, CAL2), and the single bit tine-comprising a plurality of divided bit lines (BL1, BL1 , BL2, a L Z7 ); a plurality of memory cells (MC1) each connected to a corresponding word line of said plurality of word lines and a corresponding divided bit line of the bit line of said plurality of pairs of bit lines; a plurality of sense amplifiers (SA1, SA2) provided for each of the pairs of bit lines divided into said plurality of blocks for detecting and amplifying difference between signal levels on the corresponding pair of divided bit lines after a particular word line is selected from said plurality of word lines; a plurality of restore circuits (RE1, RE2) provided for each of the pairs of bit lines divided into said plurality of blocks for detecting and further amplifying difference between signal levels amplified by said sense amplifiers (SA1, SA2) on the corresponding pair of divided bit lines; first switching means (QT1, QT2) provided for each of said divided bit lines for electrically connecting adjacent divided bit lines to each other; a control circuit for generating signals (SP1, SP2) for sequentially activating said plurality of restore circuits (RE1, RE2) in a predetermined order beginning at a restore circuit provided in a block including said selected word line; and switch control means (TG) responsive to at least control signals (SP1, SP2) to the restore circuit included in each of adjacent blocks, out of control signals from said control circuit, for controlling operation of said first switching means (QT1, QT2); said switch control means (TG) being responsive to an activating signal first generated to the restore circuits (RE1, RE2) included in adjacent blocks for rendering said first switching means (QT1, QT2) conductive.