Abstract In this data processing device, a request for direct memory-access operation is detected as one of interrupt signals. When such an interrupt is detected, a interrupt controller (10) generates a vector corresponding to the interrupt signal. On the basis of this vector, a DMA controller (20) generates a control signal showing whether the interrupt signal is a normal interrupt or an interrupt for requesting the direct memory-access operation. A CPU (30) includes a ROM (34) for storing the control function for achieving the direct memory-access operation, as micro-codes. When the DMA controller (20) generates a control signal corresponding to the interrupt signal, the CPU (30) sequentially reads out the micro-codes, to execute the direct memory-access operation. Specifically, if an interrupt for requesting the direct memory-access operation is detected, a processing space, different from that used for a normal interrupt processing, is used. The processing area has a prestorage of the data . corresponding to the data stored in various types of registers provided in the conventional DMA controller. By using this data, the data transfer is controlled by the micro-codes.
I. A data processing device comprising; interrupt detect means (10) for detecting an interrupt signal and for generating a vector (V) corresponding to the interrupt signal detected; control signal generating means (20) for generating, in response to said vector, a control signal (DMA/ INT ) which decides-whether or not said interrupt is a normal interrupt or an interrupt for requesting the direct memory-access operation; logical operation processing means (30) for storing the control function to achieve the direct memory-access operation as micro-codes, and for sequentially reading out the micro-codes when said control signal generating means generates a control signal corresponding to the interrupt signal requesting the direct memory-access operation, whereby said logical operation processing means executes and controls the direct memory-access operation; and parameter memory means (60) for storing parameters necessary for said direct memory-access operation, and for reading out these parameters in response to said vector to supply them to said logical operation processing means.
Claim 2
Dependent Claim
61 words
A data processing device according to claim I, characterized in that said control signal generating means (20) includes a register (24) for storing the data to decide whether said interrupt signal is a normal interrupt or an interrupt for requesting the direct memory-access operation, and data select means (23) for selecting the data of said register in response to said vector.
Claim 3
Dependent Claim
36 words
A data processing device according to claim I, characterized in that said logical operation processing means (30) includes at least program memory means (34) for storing the control function to achieve the direct memory-access as micro-codes.
Claim 4
Dependent Claim
48 words
A data processing device according to claim I, characterized in that said parameter memory means (60) stores commands necessary for executing and controlling the direct memory-access operation, the address of the source for data transfer, the address of the destination for data transfer, and the data transfer number.
Claim 5
Dependent Claim
20 words
A data processing device according to claim I, characterized in that said parameter memory means (60) is a read/write memory.
Claim 6
Dependent Claim
51 words
A data processing device according to claim I, characterized in that the address of the source for data transfer, the address of the destination for data transfer, and the data transfer number stored in said parameter memory means (60) are updated under the control of said logical operation processing means (30).
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