Patent EP0238406A2 successfully refreshed from Google Patents.
EP0238406A2
Expired / Lapsed
EP
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Heterojunction semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1987-03-13
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Granted: —
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Expires: 2007-03-13
Abstract
Abstract A heterojunction semiconductor device comprises an unipolar transistor comprising, a collector layer (3), a base layer (5), a collector side barrier layer (4) provided between said collector layer (3) and base layer (5), an emitter layer (8), and an emitter side barrier layer (7) provided between said base layer (5) and emitter layer (8) and having a thickness for tunneling a carrier from said emitter (8) and base (5) layers, said carrier being injected into the base layer (5) according to the application of a predetermined voltage between said emitter and base, said base layer (5) having a superlattice means (6), comprising a plurality of thin barrier layers (6B) and thin well layers (6W) for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.
Inventors
- 👤 Yuji Haishiti Omotasando 312 Awano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 20:36
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164; B; B82; B82Y; B82Y10/00; B82Y30/00; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D48/362; Y; Y10; Y10S; Y10S977/00; Y10S977/70; Y10S977/755; Y10S977/761; Y10S977/902; Y10S977/932; Y10S977/936; Y10S977/961
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
118 words
A heterojunction semiconductor device comprising; an unipolar transistor comprising; a collector layer, a base layer, a collector side barrier layer provided between said collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between said base layer and emitter layer and having a thickness for tunneling a carrier from said emitter and base layer and injected into the base layer according to applying a predetermined voltage between said emitter and base, said base layer having a superlattice means, said superlattice means comprising a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.
Claim 2
Dependent Claim
118 words
A heterojunction semiconductor device comprising; an unipolar transistor comprising; a collector layer, a base layer, a collector side barrier layer provided between said collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between said base layer and emitter layer and having a thickness for tunneling a carrier from said emitter and base layer and injected into the base layer according to applying a predetermined voltage between said emitter and base, said base layer having a superlattice means, said superlattice means comprising a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.
Claim 3
Dependent Claim
42 words
A heterojunction semiconductor device according to claim l, wherein the width of said well layer in the superlattice means is so thin that the energy level of the mini-band gap is greater than the conduction band level of said thin barrier layer.
Claim 4
Dependent Claim
20 words
A heterojunction semiconductor device according to claim 2, wherein the width of the well layer is less than 30 Å.
Claim 5
Dependent Claim
53 words
A heterojunction semiconductor device according to claim l, wherein said emitter layer is n-type semiconductor layer, said emitter side barrier layer is intrinsic type semiconductor layer or insulator layer, said base layer is n-type semiconductor layer, said collector side barrier layer is intrinsic type semiconductor layer, said collector lay is n-type semiconductor layer.
Claim 6
Dependent Claim
112 words
A heterojunction semiconductor device comprising; an unipolar transistor comprising, a collector layer, a base layer, a collector side barrier layer provided between said collector layer and base layer and an emitter layer faced with the base layer and having a smaller electron affinity than thatof the base layer, a carrier being injected from the emitter layer into the base layer by applying a predetermined voltage between said emitter and base, said base layer having a superlattice means, said superlattice means comprising a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carriers can move and a mini-band gap with which the injected carrier collides.
Claim 7
Dependent Claim
112 words
A heterojunction semiconductor device comprising; an unipolar transistor comprising, a collector layer, a base layer, a collector side barrier layer provided between said collector layer and base layer and an emitter layer faced with the base layer and having a smaller electron affinity than thatof the base layer, a carrier being injected from the emitter layer into the base layer by applying a predetermined voltage between said emitter and base, said base layer having a superlattice means, said superlattice means comprising a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carriers can move and a mini-band gap with which the injected carrier collides.
Claim 8
Dependent Claim
42 words
A heterojunction semiconductor device according to claim 5, wherein the width of said well layer in the superlattice means is so thin that the energy level of the mini-band gap is greater than the conduction band level of said thin barrier layer.
Claim 9
Dependent Claim
20 words
A heterojunction semiconductor device according to claim 5, wherein the width of the well layer is less than 30 Å.
Claim 10
Dependent Claim
53 words
A heterojunction semiconductor device according to claim 5, wherein said emitter layer is n-type semiconductor layer, said emitter side barrier layer is intrinsic type semiconductor layer or insulator layer, said base layer is n-type semiconductor layer, said collector side barrier layer is intrinsic type semiconductor layer, said collector layer is n-type semiconductor layer.
References Cited (Backward Citations)
No citation records indexed.
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