Three-dimensional integrated circuit and manufacturing method therefor

Claim 1

A semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits (A1, A2) stacked together, said unit semiconductor integrated circuit comprising:- a constituent integrated circuit on both sides of a substrate (1), a conducting post (4a, 4b) penetrating said substrate (1) and insulated therefrom, wiring (27, 42, 44) connected to an end portion of said conducting post, formed on both sides of said substrate, said wiring (27, 42, 44) formed on said constituent integrated circuit being selectively connected to said constituent integrated circuit; insulating layers (29, 45) covering both sides of said unit semiconductor integrated circuit; and interconnection terminals (6, 7) being formed on said wiring (27, 42, 44) and buried in said insulating layers (29, 45), said stacked unit semiconductor integrated circuits (A1, A2) being bonded together by means of said insulating layers (29, 45) and electrically interconnected by means of said interconnection terminals (6, 7).

Claim 7

A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits stacked together, wherein two said unit semiconductor integrated circuits (A1, A2) are connected by an interconnection terminal (6, 7) and bonded by an insulating layer (29, 45), wherein said method comprises a method of manufacturing a unit semiconductor integrated circuit, comprising the steps of:- (a) forming a plurality of holes (21, 21a, 21b) in a substrate (1) from a first surface thereof, and growing an insulating film (3) inside said holes (21) and burying a conductive material (104) therein, forming a conducting post (4, 4a, 4b); (b) forming a constituent integrated circuit on a first side of said substrate and wiring (27, 28) thereon connected selectively to an end portion of said conducting post (4, 4a, 4b); (c) coating a first insulating layer (29a, 29b) on said constituent integrated circuit and selectively forming a contact hole (31, 31a, 31b) in said first insulating layer (29a) exposing a part of said wiring and an end portion of said conducting post, and burying conductive material (106) in said contact hole forming a first interconnection terminal (6, 6a, 6b) except in a case when said unit semiconductor integrated circuit is to be used at an end position of the stack of unit semiconductor integrated circuits; (d) bonding a support plate (36) on said first surface, and polishing a second surface of the substrate until another end portion of said conducting post (4, 4a, 4b) is exposed; and (e) coating a second insulating layer (45) on a second surface of the substrate and selectively forming a contact hole in said second insulating layer and burying conductive material in said contact hole forming a second interconnection terminal (7a, 7b).