Patent EP0238089A2 successfully refreshed from Google Patents.
EP0238089A2
Expired / Lapsed
EP
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Three-dimensional integrated circuit and manufacturing method therefor
Assignee: Fujitsu Ltd
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Filing: 1987-03-20
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Granted: —
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Expires: 2007-03-20
Abstract
Abstract The invention relates to a three-dimensional IC stacked on a base plate comprising a unit semiconductor IC, A, which has each constituent IC (2a, 2b) either on a surface or on both surfaces of a substrate (1). The unit semiconductor IC has a plurality of conducting posts (4), buried in and penetrating through the substrate (1) and insulated therefrom, and also interconnection terminals (6, 7) on both sides of the substrate for connecting another unit semiconductor IC or the base plate. By stacking plural unit ICs on the base plate, a very large-scale IC can be fabricated. each constituent IC is formed on a bulk silicon substrate, so that excellent quality can be obtained. The invention can also be used for the fabrication of ROM structure such as a PROM or MASK ROM, using a single unit semiconductor IC, wherein a wiring for the ROM can be formed on a bottom surface of the substrate.
Inventors
- 👤 Takashi Fujitsu Ltd. Pat.Dep. Kato
- 👤 Masao Fujitsu Ltd. Pat.Dep. Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:56
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10D; H10D88/00; H10D88/101; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/20; H10W20/40; H10W20/481; H10W90/00; H10P72/7426; H10P72/7432; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W90/20; H10W90/284; H10W90/297
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
115 words
A semiconductor integrated circuit comprising: a plurality of unit semiconductor integrated circuits stacked together, said unit semiconductor integrated circuit comprising: a constituent integrated circuit at least on a first side of a substrate, a conducting post penetrating said substrate and insulated therefrom, wiring connected to an end portion of said conducting post, formed on one or both sides of said substrate, said wiring formed on said constituent integrated circuit being selectively connected to said constituent integrated circuit; an insulating layer bonding two said adjacent unit semiconductor integrated circuits, and covering a surface thereof; an interconnection terminal connecting two said adjacent unit semiconductor integrated circuits, being formed on said wiring and buried in said insulating layer.
Claim 2
Dependent Claim
115 words
A semiconductor integrated circuit comprising: a plurality of unit semiconductor integrated circuits stacked together, said unit semiconductor integrated circuit comprising: a constituent integrated circuit at least on a first side of a substrate, a conducting post penetrating said substrate and insulated therefrom, wiring connected to an end portion of said conducting post, formed on one or both sides of said substrate, said wiring formed on said constituent integrated circuit being selectively connected to said constituent integrated circuit; an insulating layer bonding two said adjacent unit semiconductor integrated circuits, and covering a surface thereof; an interconnection terminal connecting two said adjacent unit semiconductor integrated circuits, being formed on said wiring and buried in said insulating layer.
Claim 3
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 1, wherein said unit semiconductor integrated circuit comprises said constituent integrated circuit and said wiring on both sides of the substrate.
Claim 4
Dependent Claim
19 words
A semiconductor integrated circuit according to claim 1 or 2, wherein said insulating layer is formed of thermosetting resin.
Claim 5
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 3, wherein said thermosetting resin is Silylated Polymethylsilsesquioxane (PMSS).
Claim 6
Dependent Claim
60 words
A semiconductor integrated circuit comprising: a constituent integrated circuit on a first side of a substrate; a conducting post penetrating said substrate, being insulated therefrom, an end portion of said conducting post being selectively connected to said constituent integrated circuit; a wiring formed on a second side of said substrate, selectively connected to another end portion of said conducting post.
Claim 7
Dependent Claim
60 words
A semiconductor integrated circuit comprising: a constituent integrated circuit on a first side of a substrate; a conducting post penetrating said substrate, being insulated therefrom, an end portion of said conducting post being selectively connected to said constituent integrated circuit; a wiring formed on a second side of said substrate, selectively connected to another end portion of said conducting post.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 5, wherein said semiconductor integrated circuit forms a PROM structure and said wiring forms a power source wiring thereof.
Claim 9
Dependent Claim
48 words
A semiconductor integrated circuit according to claim 5, wherein said semiconductor integrated circuit forms a MASK ROM structure and said wiring forms a bit line of said MASK ROM, whereby a bit information is written by whether said bit line is connected to said conducting post or not.
Claim 10
Dependent Claim
52 words
A semiconductor integrated circuit according to any preceding claim, wherein a depression is formed in the substrate, surrounding an end portion of a conducting post, and an insulating layer is buried in said depression and said wiring is formed on said buried insulating layer and the end portion of the conducting post.
Claim 11
Independent Claim
252 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits stacked together, wherein two said unit semiconductor integrated circuits are connected by an interconnection terminal and bonded by an insulating layer, wherein said method comprises a method of manufacturing a unit semiconductor integrated circuit, comprising the steps of: (a) forming a plurality of holes in a substrate from a first surface thereof, and growing an insulating film inside said holes and burying a conductive material therein, forming a conducting post; (b) forming a constituent integrated circuit on a first side of said substrate and wiring thereon connected selectively to an end portion of said conducting post; (c) coating a first insulating layer on said constituent integrated circuit and selectively forming a contact hole in said first insulating layer exposing a part of said wiring and an end portion of said conducting post, and burying conductive material in said contact hole forming a first interconnection terminal except in a case when said unit semiconductor integrated circuit is to be used at an end position of the stack of unit semiconductor integrated circuits; (d) bonding a support plate on said first surface, and polishing a second surface of the substrate until another end portion of said conducting post is exposed; and (e) coating a second insulating layer on a second surface of the substrate and selectively forming a contact hole in said second insulating layer and burying conductive material in said contact hole forming a second interconnection terminal.
Claim 12
Independent Claim
252 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits stacked together, wherein two said unit semiconductor integrated circuits are connected by an interconnection terminal and bonded by an insulating layer, wherein said method comprises a method of manufacturing a unit semiconductor integrated circuit, comprising the steps of: (a) forming a plurality of holes in a substrate from a first surface thereof, and growing an insulating film inside said holes and burying a conductive material therein, forming a conducting post; (b) forming a constituent integrated circuit on a first side of said substrate and wiring thereon connected selectively to an end portion of said conducting post; (c) coating a first insulating layer on said constituent integrated circuit and selectively forming a contact hole in said first insulating layer exposing a part of said wiring and an end portion of said conducting post, and burying conductive material in said contact hole forming a first interconnection terminal except in a case when said unit semiconductor integrated circuit is to be used at an end position of the stack of unit semiconductor integrated circuits; (d) bonding a support plate on said first surface, and polishing a second surface of the substrate until another end portion of said conducting post is exposed; and (e) coating a second insulating layer on a second surface of the substrate and selectively forming a contact hole in said second insulating layer and burying conductive material in said contact hole forming a second interconnection terminal.
Claim 13
Dependent Claim
60 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits, according to claim 9, wherein said method further comprises, after step (d) and before (e), the substep of: (f) forming a constituent integrated circuit on a second surface of said substrate and wiring thereon connected selectively to an end portion of said conducting post.
Claim 14
Dependent Claim
53 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits, according to claim 9 or 10, wherein a coating process of an insulating layer in step (c) and/or step (e) further comprises the following substep of: (g) coating a thermosetting resin, for example of Silylated Polymethylsilsesquioxane (PMSS).
Claim 15
Dependent Claim
45 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits, according to claim 11, wherein the bonding process in step (d) utilizes thermoplastic resin material, having a melting temperature of higher than a curing temperature of said thermosetting resin.
Claim 16
Dependent Claim
62 words
A method of manufacturing a semiconductor integrated circuit comprising a plurality of unit semiconductor integrated circuits, according to claim 9, 10, 11 or 12, wherein the method further comprises, after step (a), the substep of: (h) forming dent surrounding both said conducting posts and filling an insulating material therein, thereby a top of said conducting post is exposed above said insulating material.
Claim 17
Independent Claim
78 words
A method of manufacturing a semiconductor integrated circuit comprising the steps of (a) forming a constituent integrated circuit on a first surface of a substrate; (b) forming a hole through a passivation layer and said substrate and growing an insulating film inside said holes of the substrate; (c) growing conductive material on the substrate, and filling said holes therewith, whereby a conducting post is formed; and (d) patterning said conductive material on said substrate, whereby wiring is formed.
Claim 18
Independent Claim
78 words
A method of manufacturing a semiconductor integrated circuit comprising the steps of (a) forming a constituent integrated circuit on a first surface of a substrate; (b) forming a hole through a passivation layer and said substrate and growing an insulating film inside said holes of the substrate; (c) growing conductive material on the substrate, and filling said holes therewith, whereby a conducting post is formed; and (d) patterning said conductive material on said substrate, whereby wiring is formed.
References Cited (Backward Citations)
No citation records indexed.
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