Hearing aid circuit

Claim 2

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter and a four pole adjustable corner highpass filter; an amplifier for receiving said filtered signal and responsively providing and an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 3

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; ; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter and an adjustable slope filter; an amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 4

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; ; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter and an adjustable slope filter; an amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 5

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said micro- phope signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter, a four pole adjustable corner highpass filter, and an adjustable slope filter; an. amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 6

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said micro- phope signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter, a four pole adjustable corner highpass filter, and an adjustable slope filter; an. amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 7

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner highpass filter and an adjustable slope filter; an amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 8

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner highpass filter and an adjustable slope filter; an amplifier for receiving said filtered signal and responsively providing an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 9

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter; an amplifier for receiving said filtered signal and responsively providing and an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 10

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner lowpass filter; an amplifier for receiving said filtered signal and responsively providing and an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 11

A hearing aid comprising, in combination; a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner highpass filter; an amplifier for receiving said filtered signal and responsively providing and an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 12

A hearing aid comprising, in combination; a microphone for receiving an input signal and providing a microphone signal; a filter for receiving and shaping said microphone signal and providing a filtered signal, said filter including a four pole adjustable corner highpass filter; an amplifier for receiving said filtered signal and responsively providing and an amplified signal; and a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 13

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a compression amplifier to compress said microphone signal and provide a compressed signal; a filter for receiving said compressed signal and providing a filtered signal; an expansion amplifier for receiving said filtered signal and responsively providing an expanded signal; a control circuit for operating said compression and expansion circuits inversely, said control circuit including a detector for receiving said compressed signal; and a receiver for receiving said expanded signal and responsively providing a sound signal.

Claim 14

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a compression amplifier to compress said microphone signal and provide a compressed signal; a filter for receiving said compressed signal and providing a filtered signal; an expansion amplifier for receiving said filtered signal and responsively providing an expanded signal; a control circuit for operating said compression and expansion circuits inversely, said control circuit including a detector for receiving said compressed signal; and a receiver for receiving said expanded signal and responsively providing a sound signal.

Claim 15

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable peak clipping circuit for receiving said microphone signal and responsively providing a clipped signal; a fixed gain output stage for receiving said clipped signal and providing an output signal; and a receiver for receiving said output signal and responsively providing a sound signal.

Claim 16

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable peak clipping circuit for receiving said microphone signal and responsively providing a clipped signal; a fixed gain output stage for receiving said clipped signal and providing an output signal; and a receiver for receiving said output signal and responsively providing a sound signal.

Claim 17

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable automatic gain control cirduit for receiving said microphone signal and responsively providing a modified signal; a fixed gain output stage for receiving said modified signal and providing an output signal; and a receiver for receiving said output signal and responsively providing a sound signal.

Claim 18

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable automatic gain control cirduit for receiving said microphone signal and responsively providing a modified signal; a fixed gain output stage for receiving said modified signal and providing an output signal; and a receiver for receiving said output signal and responsively providing a sound signal.

Claim 19

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable automatic gain control circuit for receiving said microphone signal. and responsively providing a modified signal; a fixed gain output stage for receiving said modified signal and providing an output signal; an auxiliary automatic gain control circuit for detecting the output voltage and output current of said output stage and responsively adjusting said adjustable automatic gain control circuit; and a receiver for receiving said output signal from said output stage and responsively providing a sound signal.

Claim 20

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an adjustable automatic gain control circuit for receiving said microphone signal. and responsively providing a modified signal; a fixed gain output stage for receiving said modified signal and providing an output signal; an auxiliary automatic gain control circuit for detecting the output voltage and output current of said output stage and responsively adjusting said adjustable automatic gain control circuit; and a receiver for receiving said output signal from said output stage and responsively providing a sound signal.

Claim 21

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an input automatic gain control circuit, including a primary amplifier for receiving said - microphone signal and providing a primary amplified signal in response to said microphone signal and having a variable gain controlled by a primary control signal, a secondary amplifier for receiving said microphone signal and providing a secondary amplified signal in response to said microphone signal and having a variable gain controlled by a secondary control signal, a threshold detector for sensing that said secondary amplified signal exceeds a predetermined level and responsively issuing a detected signal, a variable compression ratio control for receiving said detected signal and responsively providing a portion of said detected signal as said primary control signal to said primary amplifier, and a variable compression threshold control for providing a threshold control signal, said threshold control signal and said detected signal cooperatively defining said secondary control signal for said secondary amplifier, whereby the compression threshold and compression ratio of said primary amplifier may be independently controlled; and a receiver for receiving said primary amplified signal and responsively providing a sound signal.

Claim 22

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; an input automatic gain control circuit, including a primary amplifier for receiving said - microphone signal and providing a primary amplified signal in response to said microphone signal and having a variable gain controlled by a primary control signal, a secondary amplifier for receiving said microphone signal and providing a secondary amplified signal in response to said microphone signal and having a variable gain controlled by a secondary control signal, a threshold detector for sensing that said secondary amplified signal exceeds a predetermined level and responsively issuing a detected signal, a variable compression ratio control for receiving said detected signal and responsively providing a portion of said detected signal as said primary control signal to said primary amplifier, and a variable compression threshold control for providing a threshold control signal, said threshold control signal and said detected signal cooperatively defining said secondary control signal for said secondary amplifier, whereby the compression threshold and compression ratio of said primary amplifier may be independently controlled; and a receiver for receiving said primary amplified signal and responsively providing a sound signal.

Claim 23

A hearing aid as claimed in claim 11, further comprising in combination: a filter for receiving and shaping the frequency spectrum of said microphone signal and issuing a filtered signal; wherein said filter is positioned between said microphone and said input automatic gain control system, said input automatic gain control system receiving said filtered signal.

Claim 24

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a variable gain amplifier for receiving said microphone signal and providing an amplified signal, said amplifier exhibiting a gain, said gain being controlled by a secondary control sogma; a control signal combining natwork for receiving at least two functionally distinct primary control signals and responsively providing said secondary control signal; a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 25

A hearing aid comprising, in combination: a microphone for receiving an input signal and providing a microphone signal; a variable gain amplifier for receiving said microphone signal and providing an amplified signal, said amplifier exhibiting a gain, said gain being controlled by a secondary control sogma; a control signal combining natwork for receiving at least two functionally distinct primary control signals and responsively providing said secondary control signal; a receiver for receiving said amplified signal and responsively providing a sound signal.

Claim 26

A hearing aid as claimed in claim 13 wherein said hearing aid includes both an input automatic gain control circuit and an output automatic gain control circuit and wherein said primary control signals include an input automatic gain control signal from said input automatic gain control circuit and an output automatic gain control signal from said output automatic gain control circuit.

Claim 27

A hearing aid as claimed in Claim 13 wherein said hearing aid includes both a user-operated gain control and a compansion system and wherein said primary control signals include a user-operated gain control signal from said user-operated gain control and a compansion system control signal from said compansion system.

Claim 28

An electronic frequency filter for receiving input signal and providing filtered output signals comprising, in combinaton: a sum-difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first integrator for receizing said catput signal from said sum-difference amplifier and providing a first integrated signal; a second integrator for receiving said first integrated signal and providing a secend integrated signal; and first and second feedback lines for providing said first and second integrated signals to said sum- difference amplifier, whereby said output of said sum-difference amplifier provides a highpass filtered output signal, said first integrated signal provides a bandpass filtered output signal, and said second integrated signal provides a lowpass filtered output signal.

Claim 29

An electronic frequency filter for receiving input signal and providing filtered output signals comprising, in combinaton: a sum-difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first integrator for receizing said catput signal from said sum-difference amplifier and providing a first integrated signal; a second integrator for receiving said first integrated signal and providing a secend integrated signal; and first and second feedback lines for providing said first and second integrated signals to said sum- difference amplifier, whereby said output of said sum-difference amplifier provides a highpass filtered output signal, said first integrated signal provides a bandpass filtered output signal, and said second integrated signal provides a lowpass filtered output signal.

Claim 30

A filter as claimed in claim 16 wherein each integrator is comprised of a transconductance amplifier having an output loaded by a grounded capacitor.

Claim 31

A filter as claimed in claim 17 wherein each transconductance amplifier defines a transconductance and wherein said filter further comprises at least one control line for supplying a control current to at least one of said transconductance amplifiers, whereby said transconductance may be varied by said control current, thereby varying the characteristic frequency and quality factor of said filter.

Claim 32

A filter as claimed in claim 18, further including a control circuit with a control signal input and current means for providing two control current outputs related to said control signal input, said current means maintaining a substantially constant ratio between said two control currents as said control signal input is varied, whereby said characteristic frequency of said filter may be varied without changing the quality factor of said filter.

Claim 33

A filter as in claim 19 wherein said control circuit comprises a dual output current mirror fed by a single input control current.

Claim 34

A filter as claimed in claim 19 wherein said control circuit includes transconductance devices, each of said devices including input terminals interconnected to a single input control voltage source.

Claim 35

A filter as claimed in claim 21 in which the ratio between the two output control currents is fixed by integer numbers of identical transconductance devices connected in parallel.

Claim 36

A four pole electronic frequency filter for receiving an input signal and providing filtered output signals comprising, in combination: an input filter network including an input sum-difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first input integrator for receiving said output signal from said sum-difference amplifier and receiving a first control current and providing a first integrated signal; a second input integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal, and first and second input feedback lines for providing first and second integrated signals to said input sum-difference amplifier; an output filter network connected in cascade to said input filter network, said output filter network including an output sum-difference amplifier for receiving and combining a signal from said input signal network and two feedback signals to provide an output signal; a first output integrator for receiving said output signal from said output sum-difference amplifier and receiving a third control current and providing a first integrated signal; a second output integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal, and first and second output feedback lines for providing first and second integrated signals to said output sum-difference amplifier; a control circuit with one control signal input and four control current outputs related to the control signal input, said control circuit maintaining constant ratios between said four control current outputs as the control signal input is varied, whereby the characteristic frequencies of the filter may be varied without changing filter shape.

Claim 37

A four pole electronic frequency filter for receiving an input signal and providing filtered output signals comprising, in combination: an input filter network including an input sum-difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first input integrator for receiving said output signal from said sum-difference amplifier and receiving a first control current and providing a first integrated signal; a second input integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal, and first and second input feedback lines for providing first and second integrated signals to said input sum-difference amplifier; an output filter network connected in cascade to said input filter network, said output filter network including an output sum-difference amplifier for receiving and combining a signal from said input signal network and two feedback signals to provide an output signal; a first output integrator for receiving said output signal from said output sum-difference amplifier and receiving a third control current and providing a first integrated signal; a second output integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal, and first and second output feedback lines for providing first and second integrated signals to said output sum-difference amplifier; a control circuit with one control signal input and four control current outputs related to the control signal input, said control circuit maintaining constant ratios between said four control current outputs as the control signal input is varied, whereby the characteristic frequencies of the filter may be varied without changing filter shape.

Claim 38

An electronic frequency filter for receiving an input signal and providing filtered output signals comprising, in combination: a first filter network including a sum difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first integrator for receiving said output signal from said sum-difference amplifier and receiving a first control current and providing a first integrated signal; a second integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal and first and second input feedback lines for providing first and second integrated signals to said sum-difference amplifier; a second filter network interconnected in cascade to said first filter network and receiving at least one control current; and a control circuit with one control signal input and at least two control current outputs related to the control signal input; said control circuit maintaining constant ratios between said control current outputs as the control signal input is varied, whereby the charas--teristic frequencies of the filter may be varied without changing the filter shape.

Claim 39

An electronic frequency filter for receiving an input signal and providing filtered output signals comprising, in combination: a first filter network including a sum difference amplifier for receiving and combining said input signal and two feedback signals to provide an output signal; a first integrator for receiving said output signal from said sum-difference amplifier and receiving a first control current and providing a first integrated signal; a second integrator for receiving said first integrated signal and receiving a second control current and providing a second integrated signal and first and second input feedback lines for providing first and second integrated signals to said sum-difference amplifier; a second filter network interconnected in cascade to said first filter network and receiving at least one control current; and a control circuit with one control signal input and at least two control current outputs related to the control signal input; said control circuit maintaining constant ratios between said control current outputs as the control signal input is varied, whereby the charas--teristic frequencies of the filter may be varied without changing the filter shape.

Claim 40

A filter as claimed in claim 23 wherein said control circuit includes a four output current mirror fed by a single input control current.

Claim 41

A filter as claimed in claim 23 wherein said control circuit includes transconductance means and each of said devices has an input terminal interconnected to a single input control voltage source.

Claim 42

A filter as claimed in claim 2t wherein said transconductance means further comprises integer numbers of transconductance devices connected in parallel whereby said four output control currents define amplitudes of substantially fixed ratios.

Claim 43

A regulator for producing first and second reference voltages, whereby a slaved transconductance means having an input and having a transconductance characteristic which is in a substantially predetermined reference ratio to a reference transconductance characteristic will produce a first substantially predetermined slaved output current value while said first reference voltage is applied to said input and a second substantially predetermined slaved output current value while said second reference voltage is applied to said input, comprising, in combination: first transconductance means having a particular polarity and a first output terminal providing a first output current, said first output current being a reference current and having a first input terminal and first common terminal and having a first transconductance characteristic being said reference transconductance characteristic; second transconductance means, of same polarity as said first transconductance means, having a second output terminal providing a second output current and having a second input terminal and having a second common terminal interconnected to said first common terminal, and having a second transconductance characteristic being in a first substantially predetermined ratio to said first transconductance characteristic; third transconductance means, of an opposing polarity to said first transconductance means, having a third output terminal providing a, third output current and interconnected to said second output terminal, and having a third input terminal and third common terminal and having a third transconductance characteristic; fourth transconductance means, of same polarity as said third transconductance moans, having a fourth output terminal providing a fourth output current and interconnected to said first output terminal, and having a fourth input terminal interconnected to said third input port and having a fourth common terminal interconnected to said third common terminal, and having a fourth transconductance characteristic being in a second substantially predetermined ratio to said third transconductance characteristic, said fourth output current being in said second substantially predetermined ratio to said third output current; first amplifier means having a first amplifier input interconnected to said second and said third output terminals and having a first amplifier output, interconnected to said third and said fourth input terminals, for responsively driving said third and said fourth transconductance means such that said third output current substantially equals said second output current; fifth transconductance means, of same polarity as said first transconductance means, having a fifth output terminal providing a fifth output current and interconnected to said second input terminal, having a fifth input and a fifth common terminals respectively interconnected to said first input terminal and said first common terminal, and having a fifth transconductance characteristic being in a third substantially predetermined ratio to said first transconductance characteristic, said fifth output current being in said third substantially predetermined ratio to said first output current; second amplifier means having a second amplifier input interconnected to said fourth and said first output terminals and having a second amplfier output interconencted to said first and said fifth inp.it terminals for responsively driving said first and said fifth transconductance means such that said first output current substantially equals said fourth output current; and resistance means, having a first reference voltage output, for providing said first reference voltage, and interconnected to said fifth input terminal, and having a second reference voltage output for providing said second reference voltage and interconnected to said fifth output terminal.

Claim 44

A regulator for producing first and second reference voltages, whereby a slaved transconductance means having an input and having a transconductance characteristic which is in a substantially predetermined reference ratio to a reference transconductance characteristic will produce a first substantially predetermined slaved output current value while said first reference voltage is applied to said input and a second substantially predetermined slaved output current value while said second reference voltage is applied to said input, comprising, in combination: first transconductance means having a particular polarity and a first output terminal providing a first output current, said first output current being a reference current and having a first input terminal and first common terminal and having a first transconductance characteristic being said reference transconductance characteristic; second transconductance means, of same polarity as said first transconductance means, having a second output terminal providing a second output current and having a second input terminal and having a second common terminal interconnected to said first common terminal, and having a second transconductance characteristic being in a first substantially predetermined ratio to said first transconductance characteristic; third transconductance means, of an opposing polarity to said first transconductance means, having a third output terminal providing a, third output current and interconnected to said second output terminal, and having a third input terminal and third common terminal and having a third transconductance characteristic; fourth transconductance means, of same polarity as said third transconductance moans, having a fourth output terminal providing a fourth output current and interconnected to said first output terminal, and having a fourth input terminal interconnected to said third input port and having a fourth common terminal interconnected to said third common terminal, and having a fourth transconductance characteristic being in a second substantially predetermined ratio to said third transconductance characteristic, said fourth output current being in said second substantially predetermined ratio to said third output current; first amplifier means having a first amplifier input interconnected to said second and said third output terminals and having a first amplifier output, interconnected to said third and said fourth input terminals, for responsively driving said third and said fourth transconductance means such that said third output current substantially equals said second output current; fifth transconductance means, of same polarity as said first transconductance means, having a fifth output terminal providing a fifth output current and interconnected to said second input terminal, having a fifth input and a fifth common terminals respectively interconnected to said first input terminal and said first common terminal, and having a fifth transconductance characteristic being in a third substantially predetermined ratio to said first transconductance characteristic, said fifth output current being in said third substantially predetermined ratio to said first output current; second amplifier means having a second amplifier input interconnected to said fourth and said first output terminals and having a second amplfier output interconencted to said first and said fifth inp.it terminals for responsively driving said first and said fifth transconductance means such that said first output current substantially equals said fourth output current; and resistance means, having a first reference voltage output, for providing said first reference voltage, and interconnected to said fifth input terminal, and having a second reference voltage output for providing said second reference voltage and interconnected to said fifth output terminal.

Claim 45

A regulator as claimed in Claim 28 wherein said resistance means includes potentiometer means, having a wiper arm, for providing a variable output reference voltage which can be substantially set to a value between said first reference voltage and said second reference voltage.

Claim 46

A regulator as claimed in Claim 28 wherein all said transconductance means are transistors, having d transistor base which is said input terminal of said transconductance means, having a transistor emitter which is said common terminal of said transconductance means, and having a transistor collector, which is said output terminal of said transconductance means.

Claim 47

A regulator as claimed in claim 28 wherein said first amplifier means comprises; in combination: first and second transistors; of same polarity as said first transconductance means, interconnected substantially as a differential pair, said first transistor having a base interconnected to said first amplifier input and sensing said second and third output currents; ; said second transistor having a collector interconnected to said first amplifier output for responsively driving said third and fourth transconductance means and having a second transistor base; biasing means, interconnected to said second transistor base, for establishing a bias voltage at said second transistor base.

Claim 48

A regulator as claimed in claim 28 wherein said second amplifier means comprises, in combination: a first transistor, of same polarity as said first transconductance means, having a first transistor .base interconnected to said second amplifier input for sensing said first and fourth output currents and having a first transistor collector responsively drawing a first collector current; a second transistor, of opposing polarity to said first transistor, having a second transistor base and second transistor collector, each interconnected to said first transistor collector and having a ssecond transistor emitter; and a third transistor, of same polarity as said second transistor, having a third transistor base and third transistor emitter respectively interconnected to said second transistor base and second transistor emitter, and having a third transistor collector, interconnected to said second amplifier output, for responsively mirroring said first collector current.

Claim 49

A regulator as claimed in Claim 28 wherein said first substantially predetermined ratio of said second transconductance, to said first transconductance is substantially two to one; and said second substantially predetermined ratio of said fourth transconductance to said third transconductance is substantially three to one, whereby said first and second substantially predetermined ratios permit said slaved transconductance means, to responsively provide said first slaved output current value, while interconnected to said first reference voltage output, and to provide said second slaved output current value, while interconnected to said second reference voltage output.

Claim 50

A differential voltage threshold detector for sensing that the positive and negative values of the difference between voltages on a first input terminal and a second input terminal exceed a substantially predetermined threshold, comprising, in combination: a differential transconductance stage, with first and second differential outputs, for scnsing said voltages on said first and second input terminals and responsively issuing first and second output currents; a first top current mirror, interconnected to said first differential output, for sensing said first output current and responsively issuing first and second mirrored currents respectively from first and second mirror outputs, said first and second mirrored currents respectively being in substantially predetermined first and second ratios to said first output current; f a second top current mirror, interconnected to said second differential output, for sensing said second output current and responsively issuing third and fourth mirrored currents respectively from third and fourth mirror outputs, said third and fourth mirrored currents respectively being in substantially predetermined third and fourth ratios to said second output current; a first bottom current mirror, interconnected to said second top current mirror, for receiving said fourth mirrored current and for drawing a fifth mirrored current from a fifth mirror output, said fifth mirrored current being in a substantially predetermined fifth ratio to said fourch mirrored current; a second bottom current mirror, interconnected to said first top current mirror, for receiving said second mirrored current and for drawing a sixth mirrored current from a sixth mirror output, said sixth mirrored current being in a substantially predetermined sixth ratio to said second mirrored current; detector means, interconnected to said top and bottom current mirrors, for issuing an output signal upon sensing that (1) said first mirrored current from said first top current mirror exceeds said fifth mirrored current from said first bottom current mirror, and for issuing an output signal upon sensing that ( 2 ) said third mirrored current from said second top current mirror exceeds said sixth mirrored current from said second bottom current mirror.

Claim 51

A differential voltage threshold detector for sensing that the positive and negative values of the difference between voltages on a first input terminal and a second input terminal exceed a substantially predetermined threshold, comprising, in combination: a differential transconductance stage, with first and second differential outputs, for scnsing said voltages on said first and second input terminals and responsively issuing first and second output currents; a first top current mirror, interconnected to said first differential output, for sensing said first output current and responsively issuing first and second mirrored currents respectively from first and second mirror outputs, said first and second mirrored currents respectively being in substantially predetermined first and second ratios to said first output current; f a second top current mirror, interconnected to said second differential output, for sensing said second output current and responsively issuing third and fourth mirrored currents respectively from third and fourth mirror outputs, said third and fourth mirrored currents respectively being in substantially predetermined third and fourth ratios to said second output current; a first bottom current mirror, interconnected to said second top current mirror, for receiving said fourth mirrored current and for drawing a fifth mirrored current from a fifth mirror output, said fifth mirrored current being in a substantially predetermined fifth ratio to said fourch mirrored current; a second bottom current mirror, interconnected to said first top current mirror, for receiving said second mirrored current and for drawing a sixth mirrored current from a sixth mirror output, said sixth mirrored current being in a substantially predetermined sixth ratio to said second mirrored current; detector means, interconnected to said top and bottom current mirrors, for issuing an output signal upon sensing that (1) said first mirrored current from said first top current mirror exceeds said fifth mirrored current from said first bottom current mirror, and for issuing an output signal upon sensing that ( 2 ) said third mirrored current from said second top current mirror exceeds said sixth mirrored current from said second bottom current mirror.

Claim 52

A differential voltage detector as claimed in Claim 34 wherein said first and third ratios are substantially one to one, and said second and fourth ratios are substantially two to one; and said fifth and sixth ratios are substantially one to one.

Claim 53

A differential voltage detector as claimed in claim 34 wherein said detector means comprises, in combination: a first transconductor having a first input terminal interconnected to both said first mirror output and said fifth mirror output, and having a first output terminal and a first common terminal; and second transconductor having a second input terminal interconnected to both said third mirror output and said sixth mirror output, and having second output and common terminals interconnected respectively to said first output and common terminals, said output terminals issuing said output signal.

Claim 54

A differential voltage detector as claimed in claim 36 wherein said first and second transconductors are transistors, said input, common and output terminals being respectively, base emitter and collector terminals of said transistors.

Claim 55

A current source for providing an output current substantially exponentially related to a difference between voltages on a first input terminal and a second input terminal and substantially linearly related to an input current applied to a third input terminal comprising, in combination: a first transistor having a collector, base, and emitter, said collector being interconnected to said third input terminal, said base sensing said voltage on said first input terminal and having a first base to emitter voltage; a second transistor, having a second transistor base interconnected to said collector of said first transistor and a second transistor collector, interconnected to said emitter of said first transistor, as feedback means to regulate said first base to emitter voltage, whereby said first transistor collector current is substantially equivalent to said input current; and a third transistor, having a third transistor emitter interconnected to said emitter cf said first transistor, having a third transistor base to sense said voltage on said second input terminal, and having a third transistor collector for responsively drawing said output current.

Claim 56

A current source for providing an output current substantially exponentially related to a difference between voltages on a first input terminal and a second input terminal and substantially linearly related to an input current applied to a third input terminal comprising, in combination: a first transistor having a collector, base, and emitter, said collector being interconnected to said third input terminal, said base sensing said voltage on said first input terminal and having a first base to emitter voltage; a second transistor, having a second transistor base interconnected to said collector of said first transistor and a second transistor collector, interconnected to said emitter of said first transistor, as feedback means to regulate said first base to emitter voltage, whereby said first transistor collector current is substantially equivalent to said input current; and a third transistor, having a third transistor emitter interconnected to said emitter cf said first transistor, having a third transistor base to sense said voltage on said second input terminal, and having a third transistor collector for responsively drawing said output current.

Claim 57

A variable slope filter, for receiving an input signal at an input terminal and providing an output signal related to said input signal, comprising, in combination: first transconductance means, having an input interconnected to said input terminal, for receiving said input signal and responsively providing a first amplifier signal at a first output line, and having a feedback input interconnected to said first output line; a ground line; a capacitor interconnected between said first outpu line and said ground line; second amplifier means, interconnected to said input terminal and said first output line, for receiving said input signal and said first amplifier signal and responsively providing a second amplifier signal at a second output line; and a potentiometer, interconnected between said first and second output lines, said potentiometer including a wiper for adjusting said potentiometer, said wiper providing said output signal.

Claim 58

A variable slope filter, for receiving an input signal at an input terminal and providing an output signal related to said input signal, comprising, in combination: first transconductance means, having an input interconnected to said input terminal, for receiving said input signal and responsively providing a first amplifier signal at a first output line, and having a feedback input interconnected to said first output line; a ground line; a capacitor interconnected between said first outpu line and said ground line; second amplifier means, interconnected to said input terminal and said first output line, for receiving said input signal and said first amplifier signal and responsively providing a second amplifier signal at a second output line; and a potentiometer, interconnected between said first and second output lines, said potentiometer including a wiper for adjusting said potentiometer, said wiper providing said output signal.

Claim 59

A variable slope filter, for receiving an input signal at an input terminal and providing an output signal related to said input signal, comprising, in combination: first transductance means, interconnected to said input terminal, for receiving said input signal and responsively providing a first amplifier signal at a first output line, and having a feedback input .interconnected to said first output line; a ground line, a capacitor interconnected between said first output line and said ground line; second transconductance means, in a differential mode, with inputs interconnected between said input terminal and said first output line, for receiving said input signal and said first amplifier signal and responsively providing a second amplifier signal at a second output line; a reference voltage supply; third transconductance means, in a differential mode, with an output interconnected both to said second output line and one input, and having the other input interconnected to said reference voltage supply, for providing a load impedance for said second differential transconductance means; and a potentiometer, interconnected between said first and second ouput lines, said potentiometer including a wiper for adjusting said potentiometer, said wiper providing said output signal.

Claim 60

A variable slope filter, for receiving an input signal at an input terminal and providing an output signal related to said input signal, comprising, in combination: first transductance means, interconnected to said input terminal, for receiving said input signal and responsively providing a first amplifier signal at a first output line, and having a feedback input .interconnected to said first output line; a ground line, a capacitor interconnected between said first output line and said ground line; second transconductance means, in a differential mode, with inputs interconnected between said input terminal and said first output line, for receiving said input signal and said first amplifier signal and responsively providing a second amplifier signal at a second output line; a reference voltage supply; third transconductance means, in a differential mode, with an output interconnected both to said second output line and one input, and having the other input interconnected to said reference voltage supply, for providing a load impedance for said second differential transconductance means; and a potentiometer, interconnected between said first and second ouput lines, said potentiometer including a wiper for adjusting said potentiometer, said wiper providing said output signal.

Claim 61

A voltage clipping circuit for receiving an input signal at an input terminal and providing an output signal at an output terminal of substantially predetermined maximum amplitude comprising, in combination: first amplifier means, having an input interconnected to said input terminal and a feedback input interconnected to said output terminal, for responsively providing a first amplifier signal; second amplifier means, for receiving first amplifier signal and responsively providing said output signal, said second amplifier means including a control input for limiting maximum amplifier excursion and a variable current source for providing a control current of a predetermined magnitude to said control input and limiting said output provided by said second amplifier means.

Claim 62

A voltage clipping circuit for receiving an input signal at an input terminal and providing an output signal at an output terminal of substantially predetermined maximum amplitude comprising, in combination: first amplifier means, having an input interconnected to said input terminal and a feedback input interconnected to said output terminal, for responsively providing a first amplifier signal; second amplifier means, for receiving first amplifier signal and responsively providing said output signal, said second amplifier means including a control input for limiting maximum amplifier excursion and a variable current source for providing a control current of a predetermined magnitude to said control input and limiting said output provided by said second amplifier means.

Claim 63

A voltage clipping circuit as claimed in Claim 41 wherein said second amplifier means comprises: a transconductance amplifier which provides an output current whose maximum amplitude is controlled by said control input, and a load resistor interconnected between said output terminal and a ground line.

Claim 64

A voltage clipping circuit as claimed n. claim 42 wherein the input to said second amplifier means is an auxiliary output, whereby said first amplifier signal is provided which may be sensed by a voltage threshold detector.

Claim 65

A compansion system for increasing dynamic range of a circuit element dependent on signal ainpli- tude, said circuit element including an input lead for receiving a compressed input signal and an output lead for providing an element output signal, comprising, in combination: first amplifier means for receiving an input signal, said first amplifier means having an input signal lead, a gain control lead, and an output lead interconnected to said element input lead, said first amplifier means compressing said amplitude of said input signal with a first established function, and responsively providing a compressed input signal at said element input lead; threshold detector means. having an input lead interconnected to said element input lead and an output lead interconnected to said gain control lead of said first amplifier means, for detecting when said compressed input signal exceeds a substantially predetermined amplitude level and responsively providing a threshold signal to said gain control lead of said first amplifier means and thereby enabling said first amplifier means to reduce said amplitude by a first factor; second amplifier means, having an input signal lead, gain control lead, and output lead, for receiving signals from said output lead of said element, expanding said signal with a second established function, and responsively providing an expanded signal at said output lead; and inverse amplifier means, interconnected between said output lead of said threshold detector and said gain control lead of said second amplifier means, for receiving said threshold signal and applying a substantially inverted threshold signal to said gain control lead of said second amplifier means, whereby said amplitude of said element output signal is increased by second amplifier means by a second factor substantially equivalent to the inverse of said first factor.

Claim 66

A compansion system for increasing dynamic range of a circuit element dependent on signal ainpli- tude, said circuit element including an input lead for receiving a compressed input signal and an output lead for providing an element output signal, comprising, in combination: first amplifier means for receiving an input signal, said first amplifier means having an input signal lead, a gain control lead, and an output lead interconnected to said element input lead, said first amplifier means compressing said amplitude of said input signal with a first established function, and responsively providing a compressed input signal at said element input lead; threshold detector means. having an input lead interconnected to said element input lead and an output lead interconnected to said gain control lead of said first amplifier means, for detecting when said compressed input signal exceeds a substantially predetermined amplitude level and responsively providing a threshold signal to said gain control lead of said first amplifier means and thereby enabling said first amplifier means to reduce said amplitude by a first factor; second amplifier means, having an input signal lead, gain control lead, and output lead, for receiving signals from said output lead of said element, expanding said signal with a second established function, and responsively providing an expanded signal at said output lead; and inverse amplifier means, interconnected between said output lead of said threshold detector and said gain control lead of said second amplifier means, for receiving said threshold signal and applying a substantially inverted threshold signal to said gain control lead of said second amplifier means, whereby said amplitude of said element output signal is increased by second amplifier means by a second factor substantially equivalent to the inverse of said first factor.

Claim 67

A compansion system for increasing dynamic range of a circuit element as claimed in Claim 44 wherein said first and second amplifier means comprise variable transconductance stages, each having a resistive load and gain control lead.

Claim 68

6. A compansion system for increasing dynamic range as claimed in Claim 45 wherein said first and second amplifier means have gains which bear a substantially exponential relation to voltages applied to said gain control leads.

Claim 69

A compansion system for increasing dynamic range as claimed in Claim 46 wherein said exponential relation is generated by a system comprising a transistor whose applied base to emitter voltage is substantially equal to the said voltage applied to said gain control lead, and whose collector responsively supplies a gain control current to said variable transconductance stage wherein said gain of said variable transconductance stage is substantially linearly related to said gain control current.

Claim 70

A compansion system for increasing dynamic range of circuit element as claimed in Claim 44 wherein said circuit element is a voltage controlled filter.

Claim 71

A voltage clamp to prevent a voltage at a sense node from becoming substantially negative with respect to a reference node, said sense node joining at least two circuit elements, comprising, in combination: a substantially constant reference voltage source connected to said reference node and having a reference output node; a voltage sensor having a reference input interconnected to said reference output node for biasing purposes, a sense input interconnected to said sense node and a voltage supply input, for providing variable conductivity between said voltage supply input and said sense input, said conductivity being substantially negligible while said voltage at said sense node is greater than a substantially small positive voltage relative to said reference node, said conductivity becoming substantially large while said voltage at said sense node substantially equals zero with respect to said reference node, said conductivity becoming progressivly larger for said voltage at said sense node which is increasingly negative with respect to said reference node; and a voltage supply means, interconnected to said voltage supply input of said voltage sensor, to supply required current through said variable conductivity to said sense node.

Claim 72

A voltage clamp to prevent a voltage at a sense node from becoming substantially negative with respect to a reference node, said sense node joining at least two circuit elements, comprising, in combination: a substantially constant reference voltage source connected to said reference node and having a reference output node; a voltage sensor having a reference input interconnected to said reference output node for biasing purposes, a sense input interconnected to said sense node and a voltage supply input, for providing variable conductivity between said voltage supply input and said sense input, said conductivity being substantially negligible while said voltage at said sense node is greater than a substantially small positive voltage relative to said reference node, said conductivity becoming substantially large while said voltage at said sense node substantially equals zero with respect to said reference node, said conductivity becoming progressivly larger for said voltage at said sense node which is increasingly negative with respect to said reference node; and a voltage supply means, interconnected to said voltage supply input of said voltage sensor, to supply required current through said variable conductivity to said sense node.

Claim 73

A voltage clamp as claimed in Claim 49 wherein said-sense node joins an inductor and a collector of a transistor.

Claim 74

A voltage clamp as claimed in claim 49 wherein said reference voltage source includes a first transistor having first transistor base and first transistor collector both interconnected to said reference output node, and a first transistor emitter interconnected to said reference node, said first transistor being operated at a predetermined collector current; and wherein said voltage sensor is a second transistor having a second transistor base interconnected to saiJ reference input, having a second transistor emitter interconnected to said sense input, and a second transistor collector interconnected to said voltage supply input.

Claim 75

A voltage clamp to prevent a voltage at a sense node from becoming substantially negative with respect to a reference node, said sense node joining at least two circuit elements, comprising, in combination: a reference voltage source connected to said reference node and having a reference output node; a voltage sensor having a reference input interconnected to said reference ouput for biasing purposes, a sense input interconnected to said sense node, and a sense output for providing a sense output current, said sense output current being substantially neglibile while said voltage at said sense node is greater than a substantially small positive voltage relative to said reference node, said sense output current becoming substantially large while said voltage at said sense node substantially equals zero with respect to said reference node, said sense output current becoming progressively larger for said voltage at said sense node which is increasingly negative with respect to said reference node; and an amplified current mirror means, having a mirror input interconnected to said sense output, for receiving said sense output current and having an amplified mirror output, interconnected to said sense node, for responsively providing current to said sense node.

Claim 76

A voltage clamp to prevent a voltage at a sense node from becoming substantially negative with respect to a reference node, said sense node joining at least two circuit elements, comprising, in combination: a reference voltage source connected to said reference node and having a reference output node; a voltage sensor having a reference input interconnected to said reference ouput for biasing purposes, a sense input interconnected to said sense node, and a sense output for providing a sense output current, said sense output current being substantially neglibile while said voltage at said sense node is greater than a substantially small positive voltage relative to said reference node, said sense output current becoming substantially large while said voltage at said sense node substantially equals zero with respect to said reference node, said sense output current becoming progressively larger for said voltage at said sense node which is increasingly negative with respect to said reference node; and an amplified current mirror means, having a mirror input interconnected to said sense output, for receiving said sense output current and having an amplified mirror output, interconnected to said sense node, for responsively providing current to said sense node.

Claim 77

A voltage clamp as claimed in claim 52 wherein said reference voltage source is a first transistor having a particular polarity and having a first transistor base and first transistor collector both interconnected to said reference output node, a first transistor emitter interconnected to said reference node, said first transistor being operated at a predetermined collector current; and wherein said voltage sensor is a second transistor, of same polarity as said first transistor. having a second transistor base interconnected to said reference input, having a second transistor emitter interconnected to said sense input, and a second transistor collector interconnected to said sense output; and wherein said amplified current mirror means includes a third transistor of opposing polarity to said first transistor having third transistor base and collector both interconnected to said mirror input and having a third transistor emitter; a fourth transistor of same polarity as said third transistor, having fourth transistor base and emitter respectively interconnected to said third transistor base and said third transistor emitter, and having a fourth transistor collector; and a fifth transistor of same polarity as said first transistor having a fifth transistor base interconnected to said fourth transistor collector, and having a fifth transistor emitter interconnected to said amplified mirror output.

Claim 78

A voltage clamp as claimed in claim 53 further comprising, in combination: at least one additional sense node; at least one second additional transistor, of same polarity as said second transistor, having a second additional transistor base interconnected to said reference input; having a second additional transistor emitter interconnected to said additional sense node, and having a second additional transistor collector interconnected to said sense output; and at least one fifth additional transistor, of same polarity as said fifth transistor, having fifth additional transistor base and collector interconnected respectively to said fifth transistor base and collector, and having a fifth additional transistor emitter interconnected to said additional sense node.

Claim 79

A base bias current compensator to substantially supply base current requirements of a reference transistor which would otherwise have to be supplied by the associated circuitry, said reference transistor having a particular polarity and operating at a predetermined collector current and having-a base, and having a reference current gain characteristic, comprising, in combination: a current source for substantially supplying a current in a ratio to said predetermined collector current; a first transistor, of same polarity as said reference transistor, having a first transistor emitter interconnected to said current source, substantially receiving said current in a ratio to said predetermined collector current, and having a current gain characteristic related to said reference current gain characteristic and having a first transistor base substantially drawing a predetermined fraction of said predetermined collector current; a second transistor, of opposing polarity to said reference transistor, having a second transistor collector interconnected to said base of said first transistor for supplying a second collector current to said first transistor base, said second transistor having a second predetermined transconductance characteristic, and a second transistor base and emitter; and a third transistor, of same polarity as said second transistor, having a third transistor collector interconnected to said base of said reference transistor, for substantially supplying a predetermined base current to said base of said reference transistor, said third transistor including a base and an emitter interconnected, respectively, to said base and said emitter of said second transistor, said third transistor having a third predetermined transconductance characteristic being in a substantially predetermined ratio to said second transconductance characteristic, whereby a third collector current is provided to said base of said reference transistor which is in a predetermined ratio to said second collector current; and a feedback amplifier having an input interconnected to said first transistor emitter end an output interconnected to said bases of said second and third transistors, whereby said second collector current may be adjusted to provide said predetermined fraction of said predetermined collector current to said base of said first transistor, and whereby said third collector current is provided to said base of said reference transistor substantially in an amount required for said reference transistor to provide said predetermined collector current.

Claim 80

A base bias current compensator to substantially supply base current requirements of a reference transistor which would otherwise have to be supplied by the associated circuitry, said reference transistor having a particular polarity and operating at a predetermined collector current and having-a base, and having a reference current gain characteristic, comprising, in combination: a current source for substantially supplying a current in a ratio to said predetermined collector current; a first transistor, of same polarity as said reference transistor, having a first transistor emitter interconnected to said current source, substantially receiving said current in a ratio to said predetermined collector current, and having a current gain characteristic related to said reference current gain characteristic and having a first transistor base substantially drawing a predetermined fraction of said predetermined collector current; a second transistor, of opposing polarity to said reference transistor, having a second transistor collector interconnected to said base of said first transistor for supplying a second collector current to said first transistor base, said second transistor having a second predetermined transconductance characteristic, and a second transistor base and emitter; and a third transistor, of same polarity as said second transistor, having a third transistor collector interconnected to said base of said reference transistor, for substantially supplying a predetermined base current to said base of said reference transistor, said third transistor including a base and an emitter interconnected, respectively, to said base and said emitter of said second transistor, said third transistor having a third predetermined transconductance characteristic being in a substantially predetermined ratio to said second transconductance characteristic, whereby a third collector current is provided to said base of said reference transistor which is in a predetermined ratio to said second collector current; and a feedback amplifier having an input interconnected to said first transistor emitter end an output interconnected to said bases of said second and third transistors, whereby said second collector current may be adjusted to provide said predetermined fraction of said predetermined collector current to said base of said first transistor, and whereby said third collector current is provided to said base of said reference transistor substantially in an amount required for said reference transistor to provide said predetermined collector current.

Claim 81

A base bias current compensator as claimed in claim 55 further comprising at least one additional regulatory transistor and reference transistor, said additional reference transistor being of same polarity as said reference transistor and operating at an additional predetermined collector current, and having a base, and having an additional reference current gain characteristic being in a substantially predetermined ratio to said reference current gain characteristic, said additional regulatory transistor being of same polarity as said second transistor and having a collector substantially supplying an additional predetermined base current to said base of said additional reference transistor, said additional regulatory transistor including a base and emitter interconnected respectively to said bases and said emitters of said second and third transistors, said additonal regulatory transistor having an additional predetermined transconductance characteristic which is in an additional predetermined ratio to said second transconductance characteristic.

Claim 82

A base bias current compensator as claimed in Claim 55 wherein said feedback amplifier means includes a fourth transistor, of same polarity as said first transistor, having a fourth transistor emitter and collector respectively interconnected to said first transistor emitter and said second transistor base; and a biasing source interconnected to fourth transistor base.

Claim 83

A base bias current compensator as claimed in Claim 55 additionally comprising a fifth transistor, of same polarity as said second transistor, having fifth transistor base and collector both interconnected to said second transistor base, and fifth transistor emitter interconnected to said second transistor emitter, whereby said third collector current is less influenced by variation in current gain characteristics of said second and third transistors.

Claim 84

59 . A compression system for receiving an input signal at an input terminal and providing an output signal with a compressed dynamic range at an output terminal comprising, in combination: a primary amplifier, having an input signal lead, output lead, and primary gain control terminal, said input signal lead receiving said input signal from said input terminal, said output lead providing said output signal, said primary amplifier having a primary variable gain controlled by a primary control signal applied to said primary gain control terminal; a secondary amplifier, having an input signal lead, output lead, and secondary gain control terminal, said input signal lead receiving said input signal from said input terminal, said output lead for providing a secondary amplified signal, said secondary amplifier having a secondary variable gain controlled by a secondary control signal applied to said secondary gain control terminal;' a threshold detector means, having an input lead interconnected to said output lead of said secondary amplifier, for detecting that said secondary amplified signal exceeds a substantially predetermined amplitude level and responsively provides a detected signal; a variable threshold control for providing a threshold control signal; a control signal combining network, having at least two inputs and a control output, for receiving both said threshold signal and said detected signal at said inputs, said control signal combining network providing a control output signal at said control output, said control output being interconnected to said secondary gain control terminal and providing said secondary control signal, said secondary control signal being comprised of a combination of said detected signal and said threshold signal, whereby said threshold control signal defines said compression threshold and whereby said detected signal portion of said secondary control signal reduces said secondary variable gain such that said secondary amplified signal. does not substantially exceed said predetermined amplitude level; and a variable compression ratio control for receiving said detected signal and responsively providing a portion of said detected signal to said primary gain control terminal, said primary control signal comprising said portion of said detected signal, whereby compression threshold and compression ratio are substantially independently adjustable.

Claim 85

59 . A compression system for receiving an input signal at an input terminal and providing an output signal with a compressed dynamic range at an output terminal comprising, in combination: a primary amplifier, having an input signal lead, output lead, and primary gain control terminal, said input signal lead receiving said input signal from said input terminal, said output lead providing said output signal, said primary amplifier having a primary variable gain controlled by a primary control signal applied to said primary gain control terminal; a secondary amplifier, having an input signal lead, output lead, and secondary gain control terminal, said input signal lead receiving said input signal from said input terminal, said output lead for providing a secondary amplified signal, said secondary amplifier having a secondary variable gain controlled by a secondary control signal applied to said secondary gain control terminal;' a threshold detector means, having an input lead interconnected to said output lead of said secondary amplifier, for detecting that said secondary amplified signal exceeds a substantially predetermined amplitude level and responsively provides a detected signal; a variable threshold control for providing a threshold control signal; a control signal combining network, having at least two inputs and a control output, for receiving both said threshold signal and said detected signal at said inputs, said control signal combining network providing a control output signal at said control output, said control output being interconnected to said secondary gain control terminal and providing said secondary control signal, said secondary control signal being comprised of a combination of said detected signal and said threshold signal, whereby said threshold control signal defines said compression threshold and whereby said detected signal portion of said secondary control signal reduces said secondary variable gain such that said secondary amplified signal. does not substantially exceed said predetermined amplitude level; and a variable compression ratio control for receiving said detected signal and responsively providing a portion of said detected signal to said primary gain control terminal, said primary control signal comprising said portion of said detected signal, whereby compression threshold and compression ratio are substantially independently adjustable.

Claim 86

A compression system as claimed in Claim 59 wherein said primary and secondary amplifier means comprise variable transconductance stages, each having a resistive load and gain control terminal.

Claim 87

A compression system as claimed in Claim 60 wherein said primary and secondary amplifiers have gains which bear a substantially exponential relation to voltages applied to said gain control terminals.

Claim 88

A compression system as claimed in Claim 61 wherein said exponential relation is generated by a system comprising a transistor whose applied base to emitter voltage is substantially equal to said voltage applied to said gain control terminal and whose collector responsively supplies a gain control current to said variable transconductance stage, whereby said gain of said variable transconductance stage is substantially linearly related to said gain control current.