Patent EP0237030A2 successfully refreshed from Google Patents.
EP0237030A2
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Semiconductor memory having high-speed serial access scheme
Assignee: NEC Corp
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Filing: 1987-03-10
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Granted: —
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Expires: 2007-03-10
Abstract
Abstract A serial access semiconductor memory device operable at a high speed and having a large memory capacity is disclosed. The memory device includes a plurality of memory cells divided into a plurality of addresses including an initial address and an end address, a selection circuit for sequentially selecting the memory cells from the initial address towards the end address and a reset circuit for restarting the sequential selection from the initial address, and is featured in that the memory cell or cells of the initial address are of a static type while other memory cells are of a dynamic type.
Inventors
- 👤 Hiroshi C/O Nec Corporation Watanabe
- 👤 Takashi Asano
- 👤 Hiroaki Ikeda
- 👤 Shuichi Imazeki
- 👤 Yoshitaka Shiiya
- 👤 Yasushi Nishikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 22:25
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1039; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
90 words
A semiconductor memory device comprising a plurality of memory cells clarified into a plurality of memory addresses including an initial address and an end address, the memory cell or cells of at least said initial address being of a static type while the remaining memory cells being of a dynamic type, address means for sequentially selecting said memory cells one address by one address from said initial address towards said end address, and reset means responsive to a reset signal for controlling said address means to designate said initial address.
Claim 2
Dependent Claim
90 words
A semiconductor memory device comprising a plurality of memory cells clarified into a plurality of memory addresses including an initial address and an end address, the memory cell or cells of at least said initial address being of a static type while the remaining memory cells being of a dynamic type, address means for sequentially selecting said memory cells one address by one address from said initial address towards said end address, and reset means responsive to a reset signal for controlling said address means to designate said initial address.
Claim 3
Dependent Claim
24 words
The memory device according to claim 1, in which each of said dynamic memory cells is composed of first to third field effect transistors.
Claim 4
Dependent Claim
20 words
The memory device according to claim 1, in which said dynamic memory cells are divided into first and second sub-arrays.
Claim 5
Dependent Claim
146 words
A semiconductor memory device comprising a plurality of memory cells arranged over a plurality of addresses including an initial address to an end address, address means for sequentially selecting said memory cells one address by one address from said initial address towards said end address, a first data line for receiving data from the memory cells other than said initial address, a second data line for receiving data from the memory cell or cells of said initial address, a effective capacitance of said second data line being smaller than reset means responsive to a reset signal for having said address means select said initial address, an output circuit, and a selection circuit coupled to said first and second data lines for applying to said output circuit data on said second data line when the initial address is selected and data on said second data line otherwise.
Claim 6
Dependent Claim
146 words
A semiconductor memory device comprising a plurality of memory cells arranged over a plurality of addresses including an initial address to an end address, address means for sequentially selecting said memory cells one address by one address from said initial address towards said end address, a first data line for receiving data from the memory cells other than said initial address, a second data line for receiving data from the memory cell or cells of said initial address, a effective capacitance of said second data line being smaller than reset means responsive to a reset signal for having said address means select said initial address, an output circuit, and a selection circuit coupled to said first and second data lines for applying to said output circuit data on said second data line when the initial address is selected and data on said second data line otherwise.
Claim 7
Dependent Claim
40 words
The memory device according to claim 4, in which the memory cell or cells of said initial address are of a static type while the memory cells of the address other than said initial address are of a dynamic type.
Claim 8
Dependent Claim
41 words
The memory device according to claim 4, in which said address are divided into rows and columns and said address means includes a column selection circuit for sequentially selecting said columns, and a row selection circuit for sequentially selecting said rows.
Claim 9
Dependent Claim
101 words
A semiconductor memory device comprising a first array of static memory cells, a second array of dynamic memory cells, a read data line, first address means for sequentially selecting said static memory cells and sequentially selecting said dynamic memory cells after said static memory cells are selected. Thereby to apply to said read data line data from the selected memory cell or cells in sequence, first reset means for controlling said first address means to re-start the sequentially selecting from said static memory cell or cells in response to a first reset signal, and an output circuit for generating output data.
Claim 10
Dependent Claim
101 words
A semiconductor memory device comprising a first array of static memory cells, a second array of dynamic memory cells, a read data line, first address means for sequentially selecting said static memory cells and sequentially selecting said dynamic memory cells after said static memory cells are selected. Thereby to apply to said read data line data from the selected memory cell or cells in sequence, first reset means for controlling said first address means to re-start the sequentially selecting from said static memory cell or cells in response to a first reset signal, and an output circuit for generating output data.
Claim 11
Dependent Claim
81 words
The memory device according to claim 7, further comprising a write data line, data input means for applying input data to said write data line, second selection means for sequentially selecting said static memory cells and thereafter sequentially selecting said dynamic memory cells thereby to apply data on said write data line to the selected memory cell or cells, and second reset means for controlling said second address means to re-start the sequentially selecting from said static memory cell or cells.
References Cited (Backward Citations)
No citation records indexed.
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