Tag buffer with testing capability

Claim 2

In a circuit device, including a plurality of memory locations for storing digital data, each said location having an input and an output, said device further having control signal inputs and a single out­put, a method of testing the functionality of each of said locations, comprising the steps of: writing a predetermined pattern of digital data bits into said plurality of memory locations; disabling data inputs to all of said locations and enabling the data input of only the location to be tested; reading a data bit out of said tested location at said single output; and comparing said data bit output to said predetermined pattern data bit for said tested location

Claim 4

The method as set forth in claim 2, wherein said enabling comprises: setting the input of said tested location to said first signal level.

Claim 5

The method as set forth in claim 3, wherein said method further comprises; repeating said steps following said writing step for each of said memory locations to be tested.

Claim 6

The method as set forth in claim 3, wherein said first predetermined signal level is a digital logic LOW signal level and said second signal level is a digital logic HIGH signal level.

Claim 7

The method as set forth in claim 3, in a circuit device further having redundant memory locations used to substitute for defective memory locations, a method of testing said device to determine whether a particular location being accessed is one of said plurality of memory locations or one of said redundant locations, comprising the steps of: following said disabling and enabling step, setting a control input signal, which is set to said first level when said buffer is activated, to said third level, such that said single output will be said second signal level only when a particular location being addressed is one of said redundant locations.

Claim 9

The method as set forth in claim 7, further comprising repeating said steps following said writing step for each said parity bit location.

Claim 10

The method as set forth in claim 7, further comprising: said disabling and enabling step comprises setting a bit of control input signal, which is used to address a particular row, to a third signal level such that a data bit indicative of even parity is stored in said parity bit location; and said reading step comprises setting said control signal inputs such that said data bit indicative of even parity is transmitted to said parity checker circuit output.

Claim 11

l0. The method as set forth in claim 9, further comprising repeating said steps following said writing step for each said parity bit location.

Claim 12

In a tag buffer circuit device having digital logic control signal inputs for establishing ENABLE, WRITE and RESET modes of operation, a digital data memory component having memory cells arrayed in rows addressable via digital logic address signal inputs, said memory cells further having a data input and a data output, and said device generating an output signal at a device output terminal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of any one of said cells comprising the steps of: setting said control input signals to put said tag buffer into said WRITE mode; writing a predetermined pattern of data into said memory cell; setting said control input signals to put said tag buffer into said COMPARE mode; setting said address input signals to access a first one of said rows of memory cells; setting said data input signals to enable only a first one of said cells in said row; transmitting said data bit in said one of said cells to said device output terminal; and comparing said transmitted data bit for equality with said written predetermined pattern of data for said one of said cells.

Claim 13

In a tag buffer circuit device having digital logic control signal inputs for establishing ENABLE, WRITE and RESET modes of operation, a digital data memory component having memory cells arrayed in rows addressable via digital logic address signal inputs, said memory cells further having a data input and a data output, and said device generating an output signal at a device output terminal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of any one of said cells comprising the steps of: setting said control input signals to put said tag buffer into said WRITE mode; writing a predetermined pattern of data into said memory cell; setting said control input signals to put said tag buffer into said COMPARE mode; setting said address input signals to access a first one of said rows of memory cells; setting said data input signals to enable only a first one of said cells in said row; transmitting said data bit in said one of said cells to said device output terminal; and comparing said transmitted data bit for equality with said written predetermined pattern of data for said one of said cells.

Claim 23

2l. The method as set forth in claim l9, wherein said data bit representative of parity error is repre­sentative of even-parity in said pattern.

Claim 24

In a digital logic tag buffer integrated cir­cuit device having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural-cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of any one of said cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; storing a predetermined pattern of data into said plurality of said cells; setting said control signal inputs to digital logic levels such that said COMPARE mode is established; setting said address signal inputs to access one of said rows: setting each said cell discrete data input except the cell to be tested in said one of said rows to a digital signal level which will disable said cells; setting said cell discrete data input of said tested cell to a first digital logic level; transmitting the stored data bit in said tested cell to said output of said comparator; and comparing said transmitted bit to said prede­termined pattern bit for said tested cell for equality.

Claim 25

In a digital logic tag buffer integrated cir­cuit device having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural-cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of any one of said cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; storing a predetermined pattern of data into said plurality of said cells; setting said control signal inputs to digital logic levels such that said COMPARE mode is established; setting said address signal inputs to access one of said rows: setting each said cell discrete data input except the cell to be tested in said one of said rows to a digital signal level which will disable said cells; setting said cell discrete data input of said tested cell to a first digital logic level; transmitting the stored data bit in said tested cell to said output of said comparator; and comparing said transmitted bit to said prede­termined pattern bit for said tested cell for equality.

Claim 26

In a tag buffer integrated circuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural­cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, and each row having an additional cell for storing a bit of digital data representing the parity of a pattern of data on said data inputs, said additional cell having an input and an output, said device further having a parity generator component having a first set of discrete inputs coupled to said discrete digital data inputs and an output coupled to said additional cell, said device further having a parity checker component having an input coupled to said output of said additional cell and an output for providing a digital signal indicative of even or odd parity, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of said additional cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; writing a predetermined pattern of data into said cells such that said parity generator stores a data bit indicative of odd parity in said pattern into said additional cells in each of said rows; changing said control signal input for changing said device from said WRITE mode to said RESET mode to a third signal level; transmitting said data bit indicative of odd parity to said parity checker output; and comparing said transmitted data bit to said digital signal indicative of odd parity for equality.

Claim 27

In a tag buffer integrated circuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural­cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, and each row having an additional cell for storing a bit of digital data representing the parity of a pattern of data on said data inputs, said additional cell having an input and an output, said device further having a parity generator component having a first set of discrete inputs coupled to said discrete digital data inputs and an output coupled to said additional cell, said device further having a parity checker component having an input coupled to said output of said additional cell and an output for providing a digital signal indicative of even or odd parity, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of said additional cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; writing a predetermined pattern of data into said cells such that said parity generator stores a data bit indicative of odd parity in said pattern into said additional cells in each of said rows; changing said control signal input for changing said device from said WRITE mode to said RESET mode to a third signal level; transmitting said data bit indicative of odd parity to said parity checker output; and comparing said transmitted data bit to said digital signal indicative of odd parity for equality.

Claim 28

In a tag buffer integrated circuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic con­trol signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device fur­ther having a digital data memory storage component having a plurality of memory cells arrayed in plural­cell rows, each said row being accessible via digital logic address signal inputs to said device, each indi­vidual cell in each row having a discrete data input and output and each row having an additional cell for stor­ing a bit of digital data representing the parity of a pattern of data on said data inputs, said additional cell having an input and an output, said device further having a parity generator component having a first set of discrete inputs coupled to said discrete digital data inputs, an input coupled to one of said digital logic address signal inputs, and an output coupled to said additional cell, said device further having a parity checker component having an input coupled to said output of said additional cell and an output for providing a digital signal indicative of even or odd parity, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of said additional cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; setting said digital logic address signal input coupled to said parity generator input to a third signal level such that a data bit indicative of even parity is stored in said additional cell; setting said control signal inputs to digital logic levels such that said COMPARE mode is established; and comparing said parity checker output signal to said signal indicative of even parity for equality.

Claim 29

In a tag buffer integrated circuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic con­trol signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device fur­ther having a digital data memory storage component having a plurality of memory cells arrayed in plural­cell rows, each said row being accessible via digital logic address signal inputs to said device, each indi­vidual cell in each row having a discrete data input and output and each row having an additional cell for stor­ing a bit of digital data representing the parity of a pattern of data on said data inputs, said additional cell having an input and an output, said device further having a parity generator component having a first set of discrete inputs coupled to said discrete digital data inputs, an input coupled to one of said digital logic address signal inputs, and an output coupled to said additional cell, said device further having a parity checker component having an input coupled to said output of said additional cell and an output for providing a digital signal indicative of even or odd parity, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing the functionality of said additional cells, comprising the steps: setting said control signal inputs to digital logic levels such that said WRITE mode is established; setting said digital logic address signal input coupled to said parity generator input to a third signal level such that a data bit indicative of even parity is stored in said additional cell; setting said control signal inputs to digital logic levels such that said COMPARE mode is established; and comparing said parity checker output signal to said signal indicative of even parity for equality.

Claim 30

In a digital logic tag buffer integrated cir­cuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural-cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, said storage component having at least one redundant row for replacing any row which is defective, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing whether a particular address accesses one of said plural-cell rows or said redundant row, comprising the steps of: setting said control signal input used to establish said CHIP ENABLE mode to a third signal level; transmitting a first signal level to said comparator output if said address accesses one of said plural cell rows and a second signal level to said comparator output if said address accesses said redundant row.

Claim 31

In a digital logic tag buffer integrated cir­cuit device wherein a first signal level defines a first digital logic state and a second signal level defines a second digital logic state, having discrete digital logic control signal inputs for establishing CHIP ENABLE, WRITE, COMPARE and RESET modes of operation, said device further having a digital data memory storage component having a plurality of memory cells arrayed in plural-cell rows, each said row being accessible via digital logic address signal inputs to said device, each individual cell in each row having a discrete data input and output, said storage component having at least one redundant row for replacing any row which is defective, said device further having a comparator component having a first set of discrete inputs coupled to said discrete digital data inputs, a second set of discrete inputs coupled to said outputs of the corresponding individual cells coupled to said same discrete digital data inputs in each of said rows, and an output for providing a digital signal indicative of the equality of a data pattern on said data inputs and the content of an addressed row, a method for testing whether a particular address accesses one of said plural-cell rows or said redundant row, comprising the steps of: setting said control signal input used to establish said CHIP ENABLE mode to a third signal level; transmitting a first signal level to said comparator output if said address accesses one of said plural cell rows and a second signal level to said comparator output if said address accesses said redundant row.

Claim 32

An improved tag buffer circuit, including coupled, addressable data storage array means, parity generator and parity checker means, and comparator means, for providing a comparison of data in said array means with external data, said improvement characterized by: circuit means for testing functionality of said array means.

Claim 33

An improved tag buffer circuit, including coupled, addressable data storage array means, parity generator and parity checker means, and comparator means, for providing a comparison of data in said array means with external data, said improvement characterized by: circuit means for testing functionality of said array means.

Claim 34

The improved circuit as set forth in claim 26, further characterized by: circuit means for testing the functionality of said parity generator and parity checker means.

Claim 35

The improved circuit as set forth in claim 27, wherein said array means includes storage location means and redundant storage location means for use in place of defective storage location means, further characterized by: circuit means for determining whether an address accesses a storage location means or a redundant storage location means.